一种应用于流水线ADC的数字校正算法的改进设计

Jinghe Wei, Liming Qian, Zongguang Yu, Jiannan Yao, Longxing Shi
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引用次数: 2

摘要

数字校准算法在流水线ADC中得到越来越广泛的应用,目前基于数字校准的流水线ADC结构一般为1.5位/级。在分析了不同结构的优缺点后,本文选择了在功耗和芯片尺寸上具有较强优势的2bit/stage结构。设计了一种改进的数字校正算法,解决了现有校正算法中校正系数的精度问题,使校正后的输出数据更加准确。结果表明,改进后的数字校正算法使系统线性度得到了很大的提升。
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An improved design of digital calibration arithmetic applied in pipeline ADC
Digital calibration arithmetic becomes more and more widely applied in pipeline ADC with high precision, the structure of pipeline ADC based on digital calibration is commonly 1.5bit/stage presently. 2bit/stage, the structure of which has strong superiority in power consumption and chip size, is adopted in this paper after analyzing the advantages and disadvantages of different kinds of structures. An improved digital calibration arithmetic is designed, which has solved the problem of accuracy of calibrating coefficients in present arithmetic and made the calibrated output data more accurate. The result indicates that the improved digital calibration arithmetic makes the system linearity get highly upgraded.
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