Y. Kawano, A. Mineyama, Toshihide Suzuki, Masaru Sato, T. Hirose, K. Joshin
{"title":"全集成k波段CMOS功率放大器,Psat为23.8 dBm, PAE为25.1%","authors":"Y. Kawano, A. Mineyama, Toshihide Suzuki, Masaru Sato, T. Hirose, K. Joshin","doi":"10.1109/RFIC.2011.5940655","DOIUrl":null,"url":null,"abstract":"A fully-integrated K-band differential power amplifier was designed in 65 nm CMOS. The power amplifier comprised of the 2-stage cascode configuration has the matching networks based on the transformer. To match the impedances, turn ratios of each transformer were designed to be 1∶1 for the input stage, 2∶1 for the inter stage, and 1∶1.5 for the output stage, respectively. The saturation power of more than 20 dBm was obtained in the band between 16 GHz and 25 GHz. The peak value of the saturation power was 23.8 dBm, and the power added efficiency (PAE) was 25.1 % at 19 GHz. The chip occupied area including the DC and RF pads is 1.2 × 0.8 mm.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"A fully-integrated K-band CMOS power amplifier with Psat of 23.8 dBm and PAE of 25.1 %\",\"authors\":\"Y. Kawano, A. Mineyama, Toshihide Suzuki, Masaru Sato, T. Hirose, K. Joshin\",\"doi\":\"10.1109/RFIC.2011.5940655\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully-integrated K-band differential power amplifier was designed in 65 nm CMOS. The power amplifier comprised of the 2-stage cascode configuration has the matching networks based on the transformer. To match the impedances, turn ratios of each transformer were designed to be 1∶1 for the input stage, 2∶1 for the inter stage, and 1∶1.5 for the output stage, respectively. The saturation power of more than 20 dBm was obtained in the band between 16 GHz and 25 GHz. The peak value of the saturation power was 23.8 dBm, and the power added efficiency (PAE) was 25.1 % at 19 GHz. The chip occupied area including the DC and RF pads is 1.2 × 0.8 mm.\",\"PeriodicalId\":448165,\"journal\":{\"name\":\"2011 IEEE Radio Frequency Integrated Circuits Symposium\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Radio Frequency Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2011.5940655\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2011.5940655","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully-integrated K-band CMOS power amplifier with Psat of 23.8 dBm and PAE of 25.1 %
A fully-integrated K-band differential power amplifier was designed in 65 nm CMOS. The power amplifier comprised of the 2-stage cascode configuration has the matching networks based on the transformer. To match the impedances, turn ratios of each transformer were designed to be 1∶1 for the input stage, 2∶1 for the inter stage, and 1∶1.5 for the output stage, respectively. The saturation power of more than 20 dBm was obtained in the band between 16 GHz and 25 GHz. The peak value of the saturation power was 23.8 dBm, and the power added efficiency (PAE) was 25.1 % at 19 GHz. The chip occupied area including the DC and RF pads is 1.2 × 0.8 mm.