An efficient FPGA-based accelerator design for convolution

Number theoretic transform with the modular arithmetic operations can perform convolution efficiently in a ring without round-off errors. In this paper, a new efficient architecture of the transform have been proposed which support a various operand size. To have a balanced trade-off between area and latency, a variant constant geometry architecture is used which the forward and backward sub-stage used the same computation pattern. In addition, a XOR-based multi-ported RAM is adopted to accelerate the memory access which allow multiple simultaneous reads and writes efficiently. As a result, the developed accelerator can achieve lower area-latency FPGA compared to other designs.