{"title":"开关故障对软配置WSI成品率的影响","authors":"M. Blatt","doi":"10.1109/ICWSI.1990.63896","DOIUrl":null,"url":null,"abstract":"A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Effects of switch failure on soft-configurable WSI yield\",\"authors\":\"M. Blatt\",\"doi\":\"10.1109/ICWSI.1990.63896\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield.<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63896\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63896","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effects of switch failure on soft-configurable WSI yield
A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield.<>