{"title":"R10000微处理器的可测试性特点","authors":"J. Mori, B. Mathew, Dave Burns, Y. Mok","doi":"10.1109/ATS.1997.643930","DOIUrl":null,"url":null,"abstract":"This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Testability features of R10000 microprocessor\",\"authors\":\"J. Mori, B. Mathew, Dave Burns, Y. Mok\",\"doi\":\"10.1109/ATS.1997.643930\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented.\",\"PeriodicalId\":330767,\"journal\":{\"name\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1997.643930\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Sixth Asian Test Symposium (ATS'97)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1997.643930","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented.
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