高压LDMOS (>600V) SOI重熔结的仿真研究

Yanying Wang, Dong Zhang, Yuqiang Lv, Dawei Gong, K. Shao, Zhongjian Wang, D. He, Xinhong Cheng
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引用次数: 5

摘要

SOI上的HV LDMOS由于其优于体硅上的传统LDMOS的优点而被广泛应用于照明电子和电机控制等领域。然而,设计具有高击穿电压的优化结是公认的困难。这部分是由于缺乏结点设计的分析知识。在本研究中,利用TCAD模拟了各种结,并从半导体物理的角度进行了分析。它不仅包括高击穿电压(>600V)的结,也包括相对低击穿电压的结。通过对电场分布、静电势分布、损耗区、移动载流子等方面的比较分析,解释了某些结能获得高击穿电压的原因。此外,还研究了击穿电压与漂移区掺杂谱的关系。
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A simulation study of SOI RESURF junctions for HV LDMOS (>600V)
HV LDMOS on SOI has found wide applications such as lighting electronics and motor control due to its advantages over conventional LDMOS on bulk silicon. However, the design of optimized junctions with high breakdown voltages is commonly recognized to be difficult. This is partly because of the lack of analytical knowledge for the junctions design. In this study, various junctions were simulated by TCAD and analyzed from semiconductor physics point of view. It includes not only the junctions showing high breakdown voltages (>600V) but also the junctions showing relatively low breakdown voltages. The electrical field distribution, electrostatic potential distribution, depletion region and mobile carriers etc. were compared and analyzed to explain the reasons why a high breakdown voltage can be achieved for some junctions. Additionally, the breakdown voltage dependence on drift region doping profile was also studied.
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