{"title":"用于先进MOSFET器件的新型硅外延","authors":"G. Neudeck, T. Su, J. Denton","doi":"10.1109/IEDM.2000.904285","DOIUrl":null,"url":null,"abstract":"Silicon selective epitaxial growth (SEG) and epitaxial lateral overgrowth provide a technology for fabricating thin SOI device islands, fully self-aligned double gate SOI MOSFETs and multiple layers of SOI devices. Sub-micron P-MOSFETs in 2 SOI layers of SOI islands and the double-gate fully-depleted devices show low off currents <0.2 pA//spl mu/m with low values of sub-threshold slopes (<70 mV/dec).","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"Novel silicon epitaxy for advanced MOSFET devices\",\"authors\":\"G. Neudeck, T. Su, J. Denton\",\"doi\":\"10.1109/IEDM.2000.904285\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Silicon selective epitaxial growth (SEG) and epitaxial lateral overgrowth provide a technology for fabricating thin SOI device islands, fully self-aligned double gate SOI MOSFETs and multiple layers of SOI devices. Sub-micron P-MOSFETs in 2 SOI layers of SOI islands and the double-gate fully-depleted devices show low off currents <0.2 pA//spl mu/m with low values of sub-threshold slopes (<70 mV/dec).\",\"PeriodicalId\":276800,\"journal\":{\"name\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2000.904285\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904285","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Silicon selective epitaxial growth (SEG) and epitaxial lateral overgrowth provide a technology for fabricating thin SOI device islands, fully self-aligned double gate SOI MOSFETs and multiple layers of SOI devices. Sub-micron P-MOSFETs in 2 SOI layers of SOI islands and the double-gate fully-depleted devices show low off currents <0.2 pA//spl mu/m with low values of sub-threshold slopes (<70 mV/dec).