布局后SRAM的快速仿真模型

2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI:10.1109/ICASIC.2007.4415849

Xiaocheng Jing, R. Yao

{"title":"布局后SRAM的快速仿真模型","authors":"Xiaocheng Jing, R. Yao","doi":"10.1109/ICASIC.2007.4415849","DOIUrl":null,"url":null,"abstract":"A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A fast-simulation model for post-layout SRAM\",\"authors\":\"Xiaocheng Jing, R. Yao\",\"doi\":\"10.1109/ICASIC.2007.4415849\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415849\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415849","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

提出了一种快速、高精度的布局后静态随机存取存储器(SRAM)仿真模型。对于大容量SRAM，该模型在保持足够精度的同时，大大节省了仿真时间和布局寄生参数提取时间。对于典型的2kx32位SRAM，该模型可以节省约92%的仿真时间和约90%的布局寄生参数提取时间，同时将结果的变化保持在5%以内。

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A fast-simulation model for post-layout SRAM

A fast, high precision model for simulating post-layout static random access memory (SRAM) is presented. For large capacity SRAM, this model can greatly save both simulation time and layout parasitic parameters extraction time while keep sufficient precision. For a typical 2KX32bit SRAM, this model can save about 92% simulation time and about 90% layout parasitic parameters extraction time, while keep the result varying within 5%.

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2007 7th International Conference on ASIC

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