{"title":"比较器设计程序","authors":"C. Meixenberger, M. Degrauwe","doi":"10.1109/ESSCIRC.1988.5468352","DOIUrl":null,"url":null,"abstract":"A design program for CMOS voltage comparators based on a library of fixed schematics has been realized. The program starts from simplified analytic expressions and uses a fast built-in transient simulator in an iteration loop to converge towards a correct solution. The program takes into account device mismatches, clock feedthrough and noise which are important limitative parameters for the comparator performances. Experimental results agree with the designed values and are compared with SPICE simulation results.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Design Program for Comparators\",\"authors\":\"C. Meixenberger, M. Degrauwe\",\"doi\":\"10.1109/ESSCIRC.1988.5468352\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A design program for CMOS voltage comparators based on a library of fixed schematics has been realized. The program starts from simplified analytic expressions and uses a fast built-in transient simulator in an iteration loop to converge towards a correct solution. The program takes into account device mismatches, clock feedthrough and noise which are important limitative parameters for the comparator performances. Experimental results agree with the designed values and are compared with SPICE simulation results.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1988.5468352\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1988.5468352","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A design program for CMOS voltage comparators based on a library of fixed schematics has been realized. The program starts from simplified analytic expressions and uses a fast built-in transient simulator in an iteration loop to converge towards a correct solution. The program takes into account device mismatches, clock feedthrough and noise which are important limitative parameters for the comparator performances. Experimental results agree with the designed values and are compared with SPICE simulation results.
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