{"title":"高速硬件三月C¯","authors":"M. Saha, Souvik Das, B. Sikdar","doi":"10.1109/ISED.2012.56","DOIUrl":null,"url":null,"abstract":"The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"High Speed Hardware for March C¯\",\"authors\":\"M. Saha, Souvik Das, B. Sikdar\",\"doi\":\"10.1109/ISED.2012.56\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.\",\"PeriodicalId\":276803,\"journal\":{\"name\":\"2012 International Symposium on Electronic System Design (ISED)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Symposium on Electronic System Design (ISED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISED.2012.56\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Symposium on Electronic System Design (ISED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISED.2012.56","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.
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