{"title":"多核SIMD处理器中的电压岛设计","authors":"S. Majzoub","doi":"10.1109/IDT.2010.5724399","DOIUrl":null,"url":null,"abstract":"Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay characteristics of each instruction: slow instructions run at the nominal voltage while fast instructions run at a lower voltage to save power. An image compression algorithm is mapped into the hardware to demonstrate the power reduction. The results show energy savings of 2.0X for the specified application.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Voltage island design in multi-core SIMD processors\",\"authors\":\"S. Majzoub\",\"doi\":\"10.1109/IDT.2010.5724399\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay characteristics of each instruction: slow instructions run at the nominal voltage while fast instructions run at a lower voltage to save power. An image compression algorithm is mapped into the hardware to demonstrate the power reduction. The results show energy savings of 2.0X for the specified application.\",\"PeriodicalId\":153183,\"journal\":{\"name\":\"2010 5th International Design and Test Workshop\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 5th International Design and Test Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IDT.2010.5724399\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 5th International Design and Test Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDT.2010.5724399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Voltage island design in multi-core SIMD processors
Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay characteristics of each instruction: slow instructions run at the nominal voltage while fast instructions run at a lower voltage to save power. An image compression algorithm is mapped into the hardware to demonstrate the power reduction. The results show energy savings of 2.0X for the specified application.
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