Pub Date : 2010-12-14DOI: 10.1109/IDT.2010.5724414
M. Turki, M. Abid, Z. Marrakchi, H. Mehrez
Since their apparition, Field-Programmable Gate Arrays (FPGAs) have become the most popular implementation media for digital circuits.
现场可编程门阵列(fpga)自问世以来，已成为数字电路中最流行的实现介质。
{"title":"Routability driven placement for mesh-based FPGA architecture","authors":"M. Turki, M. Abid, Z. Marrakchi, H. Mehrez","doi":"10.1109/IDT.2010.5724414","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724414","url":null,"abstract":"Since their apparition, Field-Programmable Gate Arrays (FPGAs) have become the most popular implementation media for digital circuits.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724405
Bouthaina Damak, M. Baklouti, M. Abid
Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism impacts the SIMD architecture performance and it is closely related to the design of the processing element. In this context this paper presents a new design methodology of designing processing element for SIMD architecture. The scope of this work is to reduce the pipeline stages of the soft-core processor to reduce the size of the PEs and so that to built up a high level parallelism architecture.
{"title":"Soft-core reduction methodology for SIMD architecture: OPENRISC case study","authors":"Bouthaina Damak, M. Baklouti, M. Abid","doi":"10.1109/IDT.2010.5724405","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724405","url":null,"abstract":"Multi-Processor Systems on Chip (MPSoCs) have been proposed as a promising solution for the increasing demand of computational power required for recent application. The parallelization through SIMD (single instruction/multiple data) architectures has been a proven solution to speed up the processing of the recent application that exhibit massive amounts of data parallelism. The level of parallelism impacts the SIMD architecture performance and it is closely related to the design of the processing element. In this context this paper presents a new design methodology of designing processing element for SIMD architecture. The scope of this work is to reduce the pipeline stages of the soft-core processor to reduce the size of the PEs and so that to built up a high level parallelism architecture.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128603334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724399
S. Majzoub
Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay characteristics of each instruction: slow instructions run at the nominal voltage while fast instructions run at a lower voltage to save power. An image compression algorithm is mapped into the hardware to demonstrate the power reduction. The results show energy savings of 2.0X for the specified application.
{"title":"Voltage island design in multi-core SIMD processors","authors":"S. Majzoub","doi":"10.1109/IDT.2010.5724399","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724399","url":null,"abstract":"Today, power management is a key design objective in chip fabrication. In this paper, we present a novel approach to reduce power consumption in SIMD based multi-core architectures. Voltage scaling technique is used, by implementing voltage islands, to optimize power and performance tradeoff for the cores. The number of islands and their respective voltage are selected based on the power-delay characteristics of each instruction: slow instructions run at the nominal voltage while fast instructions run at a lower voltage to save power. An image compression algorithm is mapped into the hardware to demonstrate the power reduction. The results show energy savings of 2.0X for the specified application.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122015796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724422
Junxia Ma, M. Tehranipoor, O. Sinanoglu, S. Almukhaizim
As technology scales below 45nm and circuit integration density increases, power distribution network (PDN) contributes significantly to the total chip yield, escape, and reliability. Due to lack of controllability and observability, the PDN failure analysis has become extremely challenging. A robust PDN is essential to ensure the performance of circuits on-chip, especially for low power, high-speed designs. The area of PDN and the number of power vias and lines have dramatically increased in complex designs over the past several years resulting in increased defects on PDNs. In this paper, we present an efficient pattern generation flow that targets open defects on PDN. In this flow, the circuit layout is divided into smaller regions based on PDN structures. A vector-pair is generated to increase the region switching activity so that the gates will experience a larger-than-threshold IR-drop which may cause a timing or logic failure if only an open defect exists on power vias or power lines in that region. Various open defects on power/ground lines and vias are inserted and their impacts on circuit performance are investigated. A region sorting procedure is included in the proposed flow to reduce the computing effort. The proposed pattern generation and verification flow is implemented on ITC'99 benchmark circuit b19 and experimental results on open defect-induced IR-drop is presented and analyzed in this paper.
{"title":"Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG","authors":"Junxia Ma, M. Tehranipoor, O. Sinanoglu, S. Almukhaizim","doi":"10.1109/IDT.2010.5724422","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724422","url":null,"abstract":"As technology scales below 45nm and circuit integration density increases, power distribution network (PDN) contributes significantly to the total chip yield, escape, and reliability. Due to lack of controllability and observability, the PDN failure analysis has become extremely challenging. A robust PDN is essential to ensure the performance of circuits on-chip, especially for low power, high-speed designs. The area of PDN and the number of power vias and lines have dramatically increased in complex designs over the past several years resulting in increased defects on PDNs. In this paper, we present an efficient pattern generation flow that targets open defects on PDN. In this flow, the circuit layout is divided into smaller regions based on PDN structures. A vector-pair is generated to increase the region switching activity so that the gates will experience a larger-than-threshold IR-drop which may cause a timing or logic failure if only an open defect exists on power vias or power lines in that region. Various open defects on power/ground lines and vias are inserted and their impacts on circuit performance are investigated. A region sorting procedure is included in the proposed flow to reduce the computing effort. The proposed pattern generation and verification flow is implemented on ITC'99 benchmark circuit b19 and experimental results on open defect-induced IR-drop is presented and analyzed in this paper.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123832771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724396
Romany Sameer, A. Mohieldin, H. Eissa
Continuous scaling of CMOS devices in nm regime along with the complex processes result in increasing stress contribution in circuit performance that is no longer second order effect. Shallow Trench Isolation (STI) induced mechanical stress impacts analog designs dramatically, it is sufficient to shift bias point, change design parameters, and cause severe mismatch between transistors. This paper presents a design methodology in order to avoid stress effects in analog/mixed signal designs. This methodology flow is based on early prediction of stress effects prior to layout design to save time and avoid further costly layout iterations. Impact of STI stress on circuit performance is characterized in 40-nm CMOS technology through an op-amp and a latched comparator circuits. Furthermore, the performance after applying the proposed methodology is shown for methodology verification.
{"title":"An automated design methodology for stress avoidance in analog & mixed signal designs","authors":"Romany Sameer, A. Mohieldin, H. Eissa","doi":"10.1109/IDT.2010.5724396","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724396","url":null,"abstract":"Continuous scaling of CMOS devices in nm regime along with the complex processes result in increasing stress contribution in circuit performance that is no longer second order effect. Shallow Trench Isolation (STI) induced mechanical stress impacts analog designs dramatically, it is sufficient to shift bias point, change design parameters, and cause severe mismatch between transistors. This paper presents a design methodology in order to avoid stress effects in analog/mixed signal designs. This methodology flow is based on early prediction of stress effects prior to layout design to save time and avoid further costly layout iterations. Impact of STI stress on circuit performance is characterized in 40-nm CMOS technology through an op-amp and a latched comparator circuits. Furthermore, the performance after applying the proposed methodology is shown for methodology verification.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131491123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724412
S. Almukhaizim, M. G. Mohammad, Eman AlQuraishi
Scan-based testing of integrated circuits produces significant switching activity during shift and capture operations, dissipating excessive power levels and, possibly, resulting in an unexpected behavior of the design. The problem is further accentuated in compression-based scan; as don't care bits are exploited to compress test patterns, additional care bits are specified in the deliverable pattern, limiting the effectiveness of x-filling techniques. In this work, we propose a low-power test method for compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated, using the different encoding configurations supported by the reconfigurable scan architecture, with the objective of reducing the number of transitions during test. Hence, peak and average power of shift operation are effectively reduced. Experimental results, performed using one possible reconfigurable scan architecture as a case study, indicate that average and peak power may reduce by up to 33.8% and 26.7%, respectively, without affecting TDV and/or Test Application Time (TAT).
{"title":"Cost-free low-power test in compression-based reconfigurable scan designs","authors":"S. Almukhaizim, M. G. Mohammad, Eman AlQuraishi","doi":"10.1109/IDT.2010.5724412","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724412","url":null,"abstract":"Scan-based testing of integrated circuits produces significant switching activity during shift and capture operations, dissipating excessive power levels and, possibly, resulting in an unexpected behavior of the design. The problem is further accentuated in compression-based scan; as don't care bits are exploited to compress test patterns, additional care bits are specified in the deliverable pattern, limiting the effectiveness of x-filling techniques. In this work, we propose a low-power test method for compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated, using the different encoding configurations supported by the reconfigurable scan architecture, with the objective of reducing the number of transitions during test. Hence, peak and average power of shift operation are effectively reduced. Experimental results, performed using one possible reconfigurable scan architecture as a case study, indicate that average and peak power may reduce by up to 33.8% and 26.7%, respectively, without affecting TDV and/or Test Application Time (TAT).","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125830537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724404
Brahim Attia, Wissem Chouchene, A. Zitouni, Abid Nourdin, R. Tourki
The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how we can apply decoupling between computation and communications to achieve the IP modules and interconnections to be designed independently from each other. To validate this approach, we use AMBA AHB IPs standard at the IP side and use the most three used flow control in NoC. This NI was modeled in VHDL and implemented on Xilinx Virtex5 FPGA board. Experimental results show that the proposed Network Interfaces is feasible and efficient and it is characterized by a good performance criteria's in terms of area, power, speed, latency, and Throughput.
{"title":"Design and implementation of low latency network interface for network on chip","authors":"Brahim Attia, Wissem Chouchene, A. Zitouni, Abid Nourdin, R. Tourki","doi":"10.1109/IDT.2010.5724404","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724404","url":null,"abstract":"The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how we can apply decoupling between computation and communications to achieve the IP modules and interconnections to be designed independently from each other. To validate this approach, we use AMBA AHB IPs standard at the IP side and use the most three used flow control in NoC. This NI was modeled in VHDL and implemented on Xilinx Virtex5 FPGA board. Experimental results show that the proposed Network Interfaces is feasible and efficient and it is characterized by a good performance criteria's in terms of area, power, speed, latency, and Throughput.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122349209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724421
H. A. Abdel-Aziz, M. M. Abdel-Aziz, A. Wassal, A. Abou-Auf
In this paper, we develop a methodology for generating the worst-case test vectors (WCTV) necessary to detect leakage current failures in a standard-cell based ASIC device exposed to a total ionizing dose. The methodology is based on using the genetic algorithm technique and as such it produces a near worst-case vector. The methodology is validated experimentally by applying the generated vectors on a test chip after exposure to total dose. In terms of total-dose induced leakage current failures, experiments shown that the near worstcase vector results are very close to those of the worst-case vector.
{"title":"Worst-case test vectors generation using genetic algorithms for the detection of total-dose induced leakage current failures","authors":"H. A. Abdel-Aziz, M. M. Abdel-Aziz, A. Wassal, A. Abou-Auf","doi":"10.1109/IDT.2010.5724421","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724421","url":null,"abstract":"In this paper, we develop a methodology for generating the worst-case test vectors (WCTV) necessary to detect leakage current failures in a standard-cell based ASIC device exposed to a total ionizing dose. The methodology is based on using the genetic algorithm technique and as such it produces a near worst-case vector. The methodology is validated experimentally by applying the generated vectors on a test chip after exposure to total dose. In terms of total-dose induced leakage current failures, experiments shown that the near worstcase vector results are very close to those of the worst-case vector.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126529750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724410
W. Ibrahim, Valeriu Beiu, A. Beg
This paper provides a detailed analysis of the effects threshold voltage variations play on the reliability of bulk MOSFET transistors. It also investigates the consequences of transistor sizing on the reliability of both devices and CMOS gates. These are followed by very accurate device-level (CMOS technology specific) analyses of NOR-2 von Neumann multiplexing with respect to threshold voltage variations, taking into account both the gates' schematic as well as the input vectors. The simulation results reported here show clearly that improving the reliability at the device-level does not necessarily lead to reliability improvement at the gate- and system-level. They also reveal that the effectiveness of von Neumann multiplexing schemes depend to a great extend not only on devices, but also on the gate types (i.e., gates' topologies).
{"title":"On NOR-2 von Neumann multiplexing","authors":"W. Ibrahim, Valeriu Beiu, A. Beg","doi":"10.1109/IDT.2010.5724410","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724410","url":null,"abstract":"This paper provides a detailed analysis of the effects threshold voltage variations play on the reliability of bulk MOSFET transistors. It also investigates the consequences of transistor sizing on the reliability of both devices and CMOS gates. These are followed by very accurate device-level (CMOS technology specific) analyses of NOR-2 von Neumann multiplexing with respect to threshold voltage variations, taking into account both the gates' schematic as well as the input vectors. The simulation results reported here show clearly that improving the reliability at the device-level does not necessarily lead to reliability improvement at the gate- and system-level. They also reveal that the effectiveness of von Neumann multiplexing schemes depend to a great extend not only on devices, but also on the gate types (i.e., gates' topologies).","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133364785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-01DOI: 10.1109/IDT.2010.5724429
L. Hasan, Z. Al-Ars, M. Taouil, K. Bertels
Sequence alignment is an essential, but compute-intensive application in Bioinformatics. Hardware implementation speeds up this application by exploiting its inherent parallelism, where the performance of the hardware depends on its capability to align long sequences. In hardware terms, the length of a biological query sequence that can be aligned against a database sequence depends on the number of Processing Elements (PEs) available, which in turn depends on the amount of available hardware resources. In addition, the amount of available bandwidth to transfer the data processed by these PEs plays a significant role in defining the maximum performance. In this paper, we carry out a detailed performance and bandwidth analysis for biological sequence alignment and formulate theoretical performance boundaries for various cases. Further, we optimize the performance gain and memory bandwidth requirements and develop generalized equations for this optimization.
{"title":"Performance and bandwidth optimization for biological sequence alignment","authors":"L. Hasan, Z. Al-Ars, M. Taouil, K. Bertels","doi":"10.1109/IDT.2010.5724429","DOIUrl":"https://doi.org/10.1109/IDT.2010.5724429","url":null,"abstract":"Sequence alignment is an essential, but compute-intensive application in Bioinformatics. Hardware implementation speeds up this application by exploiting its inherent parallelism, where the performance of the hardware depends on its capability to align long sequences. In hardware terms, the length of a biological query sequence that can be aligned against a database sequence depends on the number of Processing Elements (PEs) available, which in turn depends on the amount of available hardware resources. In addition, the amount of available bandwidth to transfer the data processed by these PEs plays a significant role in defining the maximum performance. In this paper, we carry out a detailed performance and bandwidth analysis for biological sequence alignment and formulate theoretical performance boundaries for various cases. Further, we optimize the performance gain and memory bandwidth requirements and develop generalized equations for this optimization.","PeriodicalId":153183,"journal":{"name":"2010 5th International Design and Test Workshop","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125197009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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