{"title":"硅纳米电子学用肖特基势垒mosfet","authors":"J. Tucker","doi":"10.1109/WOFE.1997.621159","DOIUrl":null,"url":null,"abstract":"Metal silicide source/drain MOSFETs may provide a simple route to terabit integrated circuits with /spl sim/25 nm gate length and /spl sim/100 nm overall device size. Potential advantages of this approach are outlined here along with recent progress.","PeriodicalId":119712,"journal":{"name":"1997 Advanced Workshop on Frontiers in Electronics, WOFE '97 Proceedings","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"Schottky barrier MOSFETs for silicon nanoelectronics\",\"authors\":\"J. Tucker\",\"doi\":\"10.1109/WOFE.1997.621159\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Metal silicide source/drain MOSFETs may provide a simple route to terabit integrated circuits with /spl sim/25 nm gate length and /spl sim/100 nm overall device size. Potential advantages of this approach are outlined here along with recent progress.\",\"PeriodicalId\":119712,\"journal\":{\"name\":\"1997 Advanced Workshop on Frontiers in Electronics, WOFE '97 Proceedings\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-01-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 Advanced Workshop on Frontiers in Electronics, WOFE '97 Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WOFE.1997.621159\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Advanced Workshop on Frontiers in Electronics, WOFE '97 Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WOFE.1997.621159","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Schottky barrier MOSFETs for silicon nanoelectronics
Metal silicide source/drain MOSFETs may provide a simple route to terabit integrated circuits with /spl sim/25 nm gate length and /spl sim/100 nm overall device size. Potential advantages of this approach are outlined here along with recent progress.