{"title":"用于DAB+基带芯片的时序噪声整形解码器的硬件实现","authors":"Hongsheng Zhang, Guoyu Wang, Mingying Lu, Renyi Zhu","doi":"10.1109/COMPCOMM.2016.7925085","DOIUrl":null,"url":null,"abstract":"Advanced Audio Coding (AAC) is adopted by the Digital Audio Broadcasting plus (DAB+) system, which is the upgraded version of DAB. The increasing demand of the portable DAB+ receivers requires low-cost, low-power DAB+ baseband chip. This brings the demand of hardware-architecture AAC decoders. This paper reports a hardware implementation of the Temporal Noise Shaping (TNS) decoder, which is an important tool in AAC to eliminate the pre-echo phenomenon. The proposed TNS decoder shares the process unit with other AAC blocks to save silicon area, and uses gated clock to reduce power consumption. The design consumes only 516 logic elements and 64*18 bits ROM. It has been integrated in a DAB+ baseband chip and works well for several DAB+ receivers.","PeriodicalId":210833,"journal":{"name":"2016 2nd IEEE International Conference on Computer and Communications (ICCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hardware implementation of the Temporal Noise Shaping decoder for DAB+ baseband chip\",\"authors\":\"Hongsheng Zhang, Guoyu Wang, Mingying Lu, Renyi Zhu\",\"doi\":\"10.1109/COMPCOMM.2016.7925085\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced Audio Coding (AAC) is adopted by the Digital Audio Broadcasting plus (DAB+) system, which is the upgraded version of DAB. The increasing demand of the portable DAB+ receivers requires low-cost, low-power DAB+ baseband chip. This brings the demand of hardware-architecture AAC decoders. This paper reports a hardware implementation of the Temporal Noise Shaping (TNS) decoder, which is an important tool in AAC to eliminate the pre-echo phenomenon. The proposed TNS decoder shares the process unit with other AAC blocks to save silicon area, and uses gated clock to reduce power consumption. The design consumes only 516 logic elements and 64*18 bits ROM. It has been integrated in a DAB+ baseband chip and works well for several DAB+ receivers.\",\"PeriodicalId\":210833,\"journal\":{\"name\":\"2016 2nd IEEE International Conference on Computer and Communications (ICCC)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 2nd IEEE International Conference on Computer and Communications (ICCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMPCOMM.2016.7925085\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 2nd IEEE International Conference on Computer and Communications (ICCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMPCOMM.2016.7925085","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware implementation of the Temporal Noise Shaping decoder for DAB+ baseband chip
Advanced Audio Coding (AAC) is adopted by the Digital Audio Broadcasting plus (DAB+) system, which is the upgraded version of DAB. The increasing demand of the portable DAB+ receivers requires low-cost, low-power DAB+ baseband chip. This brings the demand of hardware-architecture AAC decoders. This paper reports a hardware implementation of the Temporal Noise Shaping (TNS) decoder, which is an important tool in AAC to eliminate the pre-echo phenomenon. The proposed TNS decoder shares the process unit with other AAC blocks to save silicon area, and uses gated clock to reduce power consumption. The design consumes only 516 logic elements and 64*18 bits ROM. It has been integrated in a DAB+ baseband chip and works well for several DAB+ receivers.