{"title":"用于标准CMOS成像应用的光电探测器结构","authors":"D. Durini, B. Hosticka","doi":"10.1109/RME.2007.4401845","DOIUrl":null,"url":null,"abstract":"In this investigation we show how a standard 0.5 mum twin-well CMOS process can be used for CMOS imaging. The process features a single-polysilicon layer, as well as three metal layers, and it is LOCOS based. We discuss various issues affecting photodetection tasks in CMOS imaging applications and present an extensive study of possible photodetector structures. Also, we propose a novel CMOS imaging pixel structure, which exceeds the standard CMOS 2-D imaging performance.","PeriodicalId":118230,"journal":{"name":"2007 Ph.D Research in Microelectronics and Electronics Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Photodetector structures for standard CMOS imaging applications\",\"authors\":\"D. Durini, B. Hosticka\",\"doi\":\"10.1109/RME.2007.4401845\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this investigation we show how a standard 0.5 mum twin-well CMOS process can be used for CMOS imaging. The process features a single-polysilicon layer, as well as three metal layers, and it is LOCOS based. We discuss various issues affecting photodetection tasks in CMOS imaging applications and present an extensive study of possible photodetector structures. Also, we propose a novel CMOS imaging pixel structure, which exceeds the standard CMOS 2-D imaging performance.\",\"PeriodicalId\":118230,\"journal\":{\"name\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-07-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 Ph.D Research in Microelectronics and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2007.4401845\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Ph.D Research in Microelectronics and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2007.4401845","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Photodetector structures for standard CMOS imaging applications
In this investigation we show how a standard 0.5 mum twin-well CMOS process can be used for CMOS imaging. The process features a single-polysilicon layer, as well as three metal layers, and it is LOCOS based. We discuss various issues affecting photodetection tasks in CMOS imaging applications and present an extensive study of possible photodetector structures. Also, we propose a novel CMOS imaging pixel structure, which exceeds the standard CMOS 2-D imaging performance.
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