{"title":"基于切比雪夫多项式插值的新型无rom直接数字频率合成器","authors":"A. Ashrafi, Z. Pan, R. Adhami, B. E. Wells","doi":"10.1109/SSST.2004.1295686","DOIUrl":null,"url":null,"abstract":"In this paper a novel ROM-less direct digital frequency synthesizer (DDFS) is introduced. The phase-to-sine mapping section of this new scheme is designed based on approximation of the first half cycle of a cosine signal by a fourth order Chebyshev polynomial. The spurious free dynamic range (SFDR) of the proposed method is 64.2 dBc while the maximum achievable SFDR is theoretically obtained equal to 66.2 dBc. The proposed method is also implemented using the Xilinx Vertex-II FPGA and the experimental results exhibit the maximum clock frequency around 25 MHz.","PeriodicalId":309617,"journal":{"name":"Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A novel ROM-less direct digital frequency synthesizer based on Chebyshev polynomial interpolation\",\"authors\":\"A. Ashrafi, Z. Pan, R. Adhami, B. E. Wells\",\"doi\":\"10.1109/SSST.2004.1295686\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a novel ROM-less direct digital frequency synthesizer (DDFS) is introduced. The phase-to-sine mapping section of this new scheme is designed based on approximation of the first half cycle of a cosine signal by a fourth order Chebyshev polynomial. The spurious free dynamic range (SFDR) of the proposed method is 64.2 dBc while the maximum achievable SFDR is theoretically obtained equal to 66.2 dBc. The proposed method is also implemented using the Xilinx Vertex-II FPGA and the experimental results exhibit the maximum clock frequency around 25 MHz.\",\"PeriodicalId\":309617,\"journal\":{\"name\":\"Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SSST.2004.1295686\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Thirty-Sixth Southeastern Symposium on System Theory, 2004. Proceedings of the","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSST.2004.1295686","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel ROM-less direct digital frequency synthesizer based on Chebyshev polynomial interpolation
In this paper a novel ROM-less direct digital frequency synthesizer (DDFS) is introduced. The phase-to-sine mapping section of this new scheme is designed based on approximation of the first half cycle of a cosine signal by a fourth order Chebyshev polynomial. The spurious free dynamic range (SFDR) of the proposed method is 64.2 dBc while the maximum achievable SFDR is theoretically obtained equal to 66.2 dBc. The proposed method is also implemented using the Xilinx Vertex-II FPGA and the experimental results exhibit the maximum clock frequency around 25 MHz.
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