ILP architectures: trading hardware for software complexity

Several interesting superscalar and VLIW (very large instruction word) processors have hit the market. These processors exploit so-called instruction level parallelism (ILP); each cycle multiple operations are executed. This paper analyzes the data path complexity of ILP processors, in particular of VLIWs. It demonstrates that their complexity gets out of control when scaling to very high performance. Several methods are researched for reducing this complexity. Essentially these methods trade hardware for software complexity, i.e., performing as much as possible at compile time. This results in a new architectural approach called transport triggering. Its concept and characteristics are outlined. The application of this concept results in a number of hardware advantages, and introduces several new scheduling optimizations.