Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651509
A. Sodan, V. Torra
The approach presented is based on a system for mapping dynamic task tree-structures, such as occur in the relevant subfields of symbolic applications, to parallel machines. This mapping system provides multiple, and in many cases combinable, elementary strategies instead of a single universal one. The strategy configuration best matching the application characteristics, i.e. leading to optimal performance, can then be chosen. This requires establishing appropriate characteristics-oriented selection criteria that are expressive and precise enough to enable the compiler to find (close-to-)optimal configurations automatically. This paper focuses on the automatic-configuration aspect and presents the FiM system's solution to this task. FiM is implemented as a fuzzy-inference system, fuzziness allowing us to capture soft classifications of application characteristics and vague certainties or degrees of adequacy about the appropriateness of strategy selections. Existing approaches to fuzzy inference had to be extended to allow fuzzy multistage reasoning. The feasibility of the fuzzy-inference approach is shown. Though developed for mapping, the FiM approach can-using the corresponding selection rules-be applied to other configuration problems in multiple-strategy systems.
{"title":"Mapping decisions by fuzzy inference","authors":"A. Sodan, V. Torra","doi":"10.1109/ICAPP.1997.651509","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651509","url":null,"abstract":"The approach presented is based on a system for mapping dynamic task tree-structures, such as occur in the relevant subfields of symbolic applications, to parallel machines. This mapping system provides multiple, and in many cases combinable, elementary strategies instead of a single universal one. The strategy configuration best matching the application characteristics, i.e. leading to optimal performance, can then be chosen. This requires establishing appropriate characteristics-oriented selection criteria that are expressive and precise enough to enable the compiler to find (close-to-)optimal configurations automatically. This paper focuses on the automatic-configuration aspect and presents the FiM system's solution to this task. FiM is implemented as a fuzzy-inference system, fuzziness allowing us to capture soft classifications of application characteristics and vague certainties or degrees of adequacy about the appropriateness of strategy selections. Existing approaches to fuzzy inference had to be extended to allow fuzzy multistage reasoning. The feasibility of the fuzzy-inference approach is shown. Though developed for mapping, the FiM approach can-using the corresponding selection rules-be applied to other configuration problems in multiple-strategy systems.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"11220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122486085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1080/01495730108941442
P. Lenders, Jingling Xue
This paper is concerned with parallelising a special class of nested loops with affine dependences. The data dependences of the program are captured in a so-called dependence matrix. Based on the eigenvalues and eigenvectors of this matrix, the proposed approach can generate a greater degree of DOALL parallelism than traditional unimodular transformations.
{"title":"Eigenvectors-based parallelisation of nested loops with affine dependences","authors":"P. Lenders, Jingling Xue","doi":"10.1080/01495730108941442","DOIUrl":"https://doi.org/10.1080/01495730108941442","url":null,"abstract":"This paper is concerned with parallelising a special class of nested loops with affine dependences. The data dependences of the program are captured in a so-called dependence matrix. Based on the eigenvalues and eigenvectors of this matrix, the proposed approach can generate a greater degree of DOALL parallelism than traditional unimodular transformations.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114362931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651486
H. Corporaal
Several interesting superscalar and VLIW (very large instruction word) processors have hit the market. These processors exploit so-called instruction level parallelism (ILP); each cycle multiple operations are executed. This paper analyzes the data path complexity of ILP processors, in particular of VLIWs. It demonstrates that their complexity gets out of control when scaling to very high performance. Several methods are researched for reducing this complexity. Essentially these methods trade hardware for software complexity, i.e., performing as much as possible at compile time. This results in a new architectural approach called transport triggering. Its concept and characteristics are outlined. The application of this concept results in a number of hardware advantages, and introduces several new scheduling optimizations.
{"title":"ILP architectures: trading hardware for software complexity","authors":"H. Corporaal","doi":"10.1109/ICAPP.1997.651486","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651486","url":null,"abstract":"Several interesting superscalar and VLIW (very large instruction word) processors have hit the market. These processors exploit so-called instruction level parallelism (ILP); each cycle multiple operations are executed. This paper analyzes the data path complexity of ILP processors, in particular of VLIWs. It demonstrates that their complexity gets out of control when scaling to very high performance. Several methods are researched for reducing this complexity. Essentially these methods trade hardware for software complexity, i.e., performing as much as possible at compile time. This results in a new architectural approach called transport triggering. Its concept and characteristics are outlined. The application of this concept results in a number of hardware advantages, and introduces several new scheduling optimizations.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651535
P.A. Hepner, W. Zhou
We put forward a distributed model for accessing heterogeneous database systems. Database operations requested by the user are processed in a distributed manner that takes advantage of the inherent parallelism of distributed systems, minimises network traffic and uses almost any general purpose computer on the network. Processing is not confined to DBMS sites but is provided as a distributed service. The design is modular and provides the mechanisms that may be arranged in a variety of ways providing a range of integration paradigms from loosely coupled integrations to more tightly coupled integrations.
{"title":"Integrating heterogeneous databases: a distributed model","authors":"P.A. Hepner, W. Zhou","doi":"10.1109/ICAPP.1997.651535","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651535","url":null,"abstract":"We put forward a distributed model for accessing heterogeneous database systems. Database operations requested by the user are processed in a distributed manner that takes advantage of the inherent parallelism of distributed systems, minimises network traffic and uses almost any general purpose computer on the network. Processing is not confined to DBMS sites but is provided as a distributed service. The design is modular and provides the mechanisms that may be arranged in a variety of ways providing a range of integration paradigms from loosely coupled integrations to more tightly coupled integrations.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124193786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651516
S. Peng, S. Sedukhin
The design of optimal array processors for solving linear systems using two-step division-free Gaussian elimination method is considered. The two-step method circumvents the one-step one in terms of numerical stability. In spite of the rather complicated computations needed at each iteration of the two-step method, we develop an innovative parallel algorithm whose data dependency graph meets the requirements for regularity and locality. Then we derive two-dimensional array processors by adopting a systematic approach to investigate the set of all admissible solutions and obtain the optimal array processors under linear time-space scheduling. The array processors is optimal in terms of the number of processing elements used.
{"title":"Parallel algorithm and architectures for two-step division-free Gaussian elimination","authors":"S. Peng, S. Sedukhin","doi":"10.1109/ICAPP.1997.651516","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651516","url":null,"abstract":"The design of optimal array processors for solving linear systems using two-step division-free Gaussian elimination method is considered. The two-step method circumvents the one-step one in terms of numerical stability. In spite of the rather complicated computations needed at each iteration of the two-step method, we develop an innovative parallel algorithm whose data dependency graph meets the requirements for regularity and locality. Then we derive two-dimensional array processors by adopting a systematic approach to investigate the set of all admissible solutions and obtain the optimal array processors under linear time-space scheduling. The array processors is optimal in terms of the number of processing elements used.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121568860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651536
Yanchun Zhang, Jitian Xiao, A. Roberts
The spatial join operations combine two sets of spatial data by their spatial relationships. They are among the most important, yet most time-consuming operations in spatial databases. We consider the problem of binary polygon intersection joins based on the filter-and-refine strategy. Our objective is to minimize the I/O cost and the response time for the refinement step. First, a graph model is proposed to formalize the refinement cost and matrix-based sequential data partition algorithms are introduced. Then a parallel data partitioning algorithm is developed with a detailed complexity analysis. Based on the data partition results, a distribution algorithm is also proposed for scheduling parallel spatial join processing.
{"title":"Parallel algorithms for spatial data partition and join processing","authors":"Yanchun Zhang, Jitian Xiao, A. Roberts","doi":"10.1109/ICAPP.1997.651536","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651536","url":null,"abstract":"The spatial join operations combine two sets of spatial data by their spatial relationships. They are among the most important, yet most time-consuming operations in spatial databases. We consider the problem of binary polygon intersection joins based on the filter-and-refine strategy. Our objective is to minimize the I/O cost and the response time for the refinement step. First, a graph model is proposed to formalize the refinement cost and matrix-based sequential data partition algorithms are introduced. Then a parallel data partitioning algorithm is developed with a detailed complexity analysis. Based on the data partition results, a distribution algorithm is also proposed for scheduling parallel spatial join processing.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114691927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651482
J. Huang, G. Jin, Zhiyuan Li
Careful page mapping has been shown in the past to be effective for reducing cache conflicts on both uniprocessor and Uniform Memory Access (UMA) multiprocessors. This paper extends previous page-mapping schemes to the more recent Cache-Coherent Non-Uniform Memory Access (CC-NUMA) multiprocessors. These extensions maintain the program's data-task affinity, which is important to CC-NUMA, while reducing cache set conflicts by carefully selecting the page frames. Using an execution-driven simulator that simulates a CC-NUMA machine with a 4-MB secondary cache and a 16-KB primary cache on each of the 4-issue super-scalar processors, we find that, when non-coherence cache misses are relatively heavy, it is quite important for page mapping to preserve the compiler-generated memory module ID (MID) which determines data distribution among the processors. We also find that straight application of page-coloring performs worse than bin-hopping by 10-45%, while by hashing the page color with part of the MID, page-coloring can perform closely to bin-hopping.
{"title":"Page-mapping techniques for CC-NUMA multiprocessors","authors":"J. Huang, G. Jin, Zhiyuan Li","doi":"10.1109/ICAPP.1997.651482","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651482","url":null,"abstract":"Careful page mapping has been shown in the past to be effective for reducing cache conflicts on both uniprocessor and Uniform Memory Access (UMA) multiprocessors. This paper extends previous page-mapping schemes to the more recent Cache-Coherent Non-Uniform Memory Access (CC-NUMA) multiprocessors. These extensions maintain the program's data-task affinity, which is important to CC-NUMA, while reducing cache set conflicts by carefully selecting the page frames. Using an execution-driven simulator that simulates a CC-NUMA machine with a 4-MB secondary cache and a 16-KB primary cache on each of the 4-issue super-scalar processors, we find that, when non-coherence cache misses are relatively heavy, it is quite important for page mapping to preserve the compiler-generated memory module ID (MID) which determines data distribution among the processors. We also find that straight application of page-coloring performs worse than bin-hopping by 10-45%, while by hashing the page color with part of the MID, page-coloring can perform closely to bin-hopping.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115809505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651510
M. De Simone, Ashutosh Kumar Singh
Active Expressions (A/sub e/) is a language-based model for the instantiation of type-safe concurrent applications. Using facilities included in modern object-oriented languages, Ae allows the definition of communication and synchronization patterns that, when combined with user provided functionality through well defined interfaces, instantiate complete concurrent applications. The approach has two unique characteristics: First, it shows that common patterns of concurrency can be expressed using language provided facilities. Second, the model can be implemented without requiring any complex user-interfaces, preprocessing stages or language extensions. It also shows that the pattern-based approach has the potential to reduce the complexity of developing concurrent applications.
Active Expressions (A/sub / e/)是一种基于语言的模型，用于实例化类型安全的并发应用程序。使用现代面向对象语言中包含的功能，Ae允许定义通信和同步模式，当通过定义良好的接口与用户提供的功能相结合时，可以实例化完整的并发应用程序。该方法有两个独特的特点:首先，它表明可以使用语言提供的工具来表示常见的并发模式。其次，模型可以在不需要任何复杂的用户界面、预处理阶段或语言扩展的情况下实现。它还表明，基于模式的方法具有降低并发应用程序开发复杂性的潜力。
{"title":"Active Expressions: a framework for concurrency","authors":"M. De Simone, Ashutosh Kumar Singh","doi":"10.1109/ICAPP.1997.651510","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651510","url":null,"abstract":"Active Expressions (A/sub e/) is a language-based model for the instantiation of type-safe concurrent applications. Using facilities included in modern object-oriented languages, Ae allows the definition of communication and synchronization patterns that, when combined with user provided functionality through well defined interfaces, instantiate complete concurrent applications. The approach has two unique characteristics: First, it shows that common patterns of concurrency can be expressed using language provided facilities. Second, the model can be implemented without requiring any complex user-interfaces, preprocessing stages or language extensions. It also shows that the pattern-based approach has the potential to reduce the complexity of developing concurrent applications.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132840842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651518
Sam Lin, Rynson W. H. Lau, X. Lin, P. Cheung
Original z-buffer method is a very efficient method for image generation. The limitation is that it introduces aliases into the output image. Although many methods have been proposed to address this problem. Most of them suffer from requiring a large memory space, demanding for high computational power, or having some other limitations. Recently, we presented a simple anti-aliasing method based on the supersampling method. Instead of supersampling every pixel, we supersample edge pixels only. In this paper, we discuss various approaches for parallelizing the method and their effects on memory usage and performance.
{"title":"A parallel rendering approach to the adaptive supersampling method","authors":"Sam Lin, Rynson W. H. Lau, X. Lin, P. Cheung","doi":"10.1109/ICAPP.1997.651518","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651518","url":null,"abstract":"Original z-buffer method is a very efficient method for image generation. The limitation is that it introduces aliases into the output image. Although many methods have been proposed to address this problem. Most of them suffer from requiring a large memory space, demanding for high computational power, or having some other limitations. Recently, we presented a simple anti-aliasing method based on the supersampling method. Instead of supersampling every pixel, we supersample edge pixels only. In this paper, we discuss various approaches for parallelizing the method and their effects on memory usage and performance.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128566894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-10DOI: 10.1109/ICAPP.1997.651524
C. Thomborson
We propose and justify an economic theory to guide memory system design, operation and analysis. Our theory treats memory random-access latency, and its cost per installed megabyte, as fundamentals. We introduce incentives in our economic theory, and side-constraints in our analytic model of hierarchical memory to ensure sufficient memory bandwidth and processor speed in any "well-formed" system of a given latency and size. We suggest, on the basis of our theory, that computer users should be charged a "rental" cost, proportional to their use of the total capacity in a hierarchical memory system. Finally, we use our theory to compare the cost/performance of various large-memory organisations such as PoPCs (piles of PCs), NOWs (networks of workstations), SMPs (shared memory multiprocessors), MPPs (massively parallel processors), and even Cray-class vector supercomputers.
{"title":"The economics of large-memory computations","authors":"C. Thomborson","doi":"10.1109/ICAPP.1997.651524","DOIUrl":"https://doi.org/10.1109/ICAPP.1997.651524","url":null,"abstract":"We propose and justify an economic theory to guide memory system design, operation and analysis. Our theory treats memory random-access latency, and its cost per installed megabyte, as fundamentals. We introduce incentives in our economic theory, and side-constraints in our analytic model of hierarchical memory to ensure sufficient memory bandwidth and processor speed in any \"well-formed\" system of a given latency and size. We suggest, on the basis of our theory, that computer users should be charged a \"rental\" cost, proportional to their use of the total capacity in a hierarchical memory system. Finally, we use our theory to compare the cost/performance of various large-memory organisations such as PoPCs (piles of PCs), NOWs (networks of workstations), SMPs (shared memory multiprocessors), MPPs (massively parallel processors), and even Cray-class vector supercomputers.","PeriodicalId":325978,"journal":{"name":"Proceedings of 3rd International Conference on Algorithms and Architectures for Parallel Processing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127879552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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