{"title":"CMOS宽摆差压控振荡器完全集成快速锁相环","authors":"Y. Fouzar, M. Sawan, Y. Savaria","doi":"10.1109/MWSCAS.2000.952910","DOIUrl":null,"url":null,"abstract":"Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"CMOS wide-swing differential VCO for fully integrated fast PLL\",\"authors\":\"Y. Fouzar, M. Sawan, Y. Savaria\",\"doi\":\"10.1109/MWSCAS.2000.952910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.\",\"PeriodicalId\":437349,\"journal\":{\"name\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"volume\":\"244 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2000.952910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.952910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS wide-swing differential VCO for fully integrated fast PLL
Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.