{"title":"盲自适应天线的FPGA实现","authors":"A. Boonpoonga, P. Sirisuk, M. Krairiksh","doi":"10.1109/IEECON.2014.6925958","DOIUrl":null,"url":null,"abstract":"This paper presents a review of an adaptive array antenna using a constant modulus algorithm (CMA) in implementation aspect. MAC and parallel architectures of the CMA processing unit for the adaptive antenna are discussed. The CMA processing units based on MAC or parallel architecture is implemented on field programmable gate array (FPGA). The effect of floating-point and fixed-point arithmetic on the performance of the CMA processing unit is also discussed. Finally, the FPGA resource utilization and maximum operating clock frequency are shown.","PeriodicalId":306512,"journal":{"name":"2014 International Electrical Engineering Congress (iEECON)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"On FPGA implementation of blind adaptive antenna\",\"authors\":\"A. Boonpoonga, P. Sirisuk, M. Krairiksh\",\"doi\":\"10.1109/IEECON.2014.6925958\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a review of an adaptive array antenna using a constant modulus algorithm (CMA) in implementation aspect. MAC and parallel architectures of the CMA processing unit for the adaptive antenna are discussed. The CMA processing units based on MAC or parallel architecture is implemented on field programmable gate array (FPGA). The effect of floating-point and fixed-point arithmetic on the performance of the CMA processing unit is also discussed. Finally, the FPGA resource utilization and maximum operating clock frequency are shown.\",\"PeriodicalId\":306512,\"journal\":{\"name\":\"2014 International Electrical Engineering Congress (iEECON)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-03-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Electrical Engineering Congress (iEECON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEECON.2014.6925958\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Electrical Engineering Congress (iEECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEECON.2014.6925958","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a review of an adaptive array antenna using a constant modulus algorithm (CMA) in implementation aspect. MAC and parallel architectures of the CMA processing unit for the adaptive antenna are discussed. The CMA processing units based on MAC or parallel architecture is implemented on field programmable gate array (FPGA). The effect of floating-point and fixed-point arithmetic on the performance of the CMA processing unit is also discussed. Finally, the FPGA resource utilization and maximum operating clock frequency are shown.