{"title":"一种宽范围突发模式时钟和数据恢复电路","authors":"Wei-Zen Chen, Chin-Yuan Wei, Jennie Chen","doi":"10.1109/ASSCC.2006.357936","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10-10.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Wide-Range Burst Mode Clock and Data Recovery Circuit\",\"authors\":\"Wei-Zen Chen, Chin-Yuan Wei, Jennie Chen\",\"doi\":\"10.1109/ASSCC.2006.357936\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10-10.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357936\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357936","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Wide-Range Burst Mode Clock and Data Recovery Circuit
This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 mum CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10-10.
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