{"title":"用于20mhz NMOS A/D转换器的5位构建块","authors":"H. Fiedler, B. Hoefflinger, W. Demmer, P. Draheim","doi":"10.1109/ESSCIRC.1980.5468812","DOIUrl":null,"url":null,"abstract":"This paper presents a monolithic, fully parallel 5-bit NMOS A/D converter. The chip is fabricated using a standard metal-gate enhancement/depletion technology with 7 μm minimum features. It contains 31 strobed comparators, latches, combinational logic, a 5 by 31 ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step 8-bit converters. The chip was fully characterised at 20 megasamples per seconds. The dc linearity was better than 1/4 LSB for 80 mV step size.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 5-Bit Building Block for 20 MHz NMOS A/D Converters\",\"authors\":\"H. Fiedler, B. Hoefflinger, W. Demmer, P. Draheim\",\"doi\":\"10.1109/ESSCIRC.1980.5468812\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a monolithic, fully parallel 5-bit NMOS A/D converter. The chip is fabricated using a standard metal-gate enhancement/depletion technology with 7 μm minimum features. It contains 31 strobed comparators, latches, combinational logic, a 5 by 31 ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step 8-bit converters. The chip was fully characterised at 20 megasamples per seconds. The dc linearity was better than 1/4 LSB for 80 mV step size.\",\"PeriodicalId\":168272,\"journal\":{\"name\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1980.5468812\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
本文提出了一种单片全并行5位NMOS a /D转换器。该芯片采用最小特征为7 μm的标准金属栅增强/耗尽技术制造。它包含31个频闪比较器、锁存器、组合逻辑、一个5 × 31 ROM、TTL缓冲器和一个4位DAC。这使它成为两步8位转换器的构建块。该芯片以每秒20兆样本的速度被完全表征。当步长为80 mV时，直流线性度优于1/4 LSB。
A 5-Bit Building Block for 20 MHz NMOS A/D Converters
This paper presents a monolithic, fully parallel 5-bit NMOS A/D converter. The chip is fabricated using a standard metal-gate enhancement/depletion technology with 7 μm minimum features. It contains 31 strobed comparators, latches, combinational logic, a 5 by 31 ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step 8-bit converters. The chip was fully characterised at 20 megasamples per seconds. The dc linearity was better than 1/4 LSB for 80 mV step size.
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