Analysis of Chopper Ripple Reduction by Delayed Sampling

Chopping is widely used to mitigate 1/f noise and offset of amplifiers, e.g., in implantable biomedical devices where very-low-frequency signals are of interest. The main disadvantages of chopping is the degradation of input impedance and the presence of chopping ripples superposing the recorded neural signal. These ripples are especially critical in sampled systems, as back-folding into the baseband should be avoided. Additionally, loop linearity and stability can be compromised by chopping ripples in feedback systems. This article compares ripple reduction strategies from prior art and presents a mathematical analysis of a simple and effective technique by delayed sampling. A description of the signal chain is derived in order to develop a model, which is subsequently used to demonstrate the effectiveness of the presented method. System-level simulations verify the functionality and yield a 30 dB ripple reduction at virtually no additional hardware expense.