{"title":"单片运动JPEG编解码器LSI","authors":"Okada, Matsuda, Watanabe, Kondo","doi":"10.1109/30.628651","DOIUrl":null,"url":null,"abstract":"We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels/spl times/480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.","PeriodicalId":127085,"journal":{"name":"1997 International Conference on Consumer Electronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A Single Chip Motion JPEG Codec LSI\",\"authors\":\"Okada, Matsuda, Watanabe, Kondo\",\"doi\":\"10.1109/30.628651\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels/spl times/480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.\",\"PeriodicalId\":127085,\"journal\":{\"name\":\"1997 International Conference on Consumer Electronics\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/30.628651\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/30.628651","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels/spl times/480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products.
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