A new design for high speed and high-density carry select adders

An algorithm with logarithmic carry propagation delay is developed for high-density adders. The design procedure is introduced for the construction of a 64-bit adder with maximum path delay equivalent to 8 gate delays. The algorithm is based on the carry select technique with operands partitioned into very fine slices for both quick response and low gate counts. Another property observed in this algorithm is resource (hardware) sharing which is due to regularity of the carry channel structure. The design is coded in Verilog, simulated and implemented using XC4010E Xilinx FPGA technology.