{"title":"基于FPGA的快速QR分解","authors":"S. Omran, Ahmed K. Abdul-abbas","doi":"10.1109/ICOASE.2018.8548895","DOIUrl":null,"url":null,"abstract":"The QR-decomposition (QRD) is an implementation necessary for many different detection algorithms such as MIMO (Multiple Input and Multiple Output) in wireless communication system. In this article, a QRD processor which decomposes the matrix into an orthogonal (Q matrix) and upper triangular matrix (R matrix) using Gram Schmidt algorithm is designed and implemented using a 32-bit High speed processor based on FPGA. This design requires 16 clock cycle to compute QR decomposition with 15.625 M QRDs per second throughput at 250 MHz operating frequency.","PeriodicalId":144020,"journal":{"name":"2018 International Conference on Advanced Science and Engineering (ICOASE)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Fast QR Decomposition Based on FPGA\",\"authors\":\"S. Omran, Ahmed K. Abdul-abbas\",\"doi\":\"10.1109/ICOASE.2018.8548895\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The QR-decomposition (QRD) is an implementation necessary for many different detection algorithms such as MIMO (Multiple Input and Multiple Output) in wireless communication system. In this article, a QRD processor which decomposes the matrix into an orthogonal (Q matrix) and upper triangular matrix (R matrix) using Gram Schmidt algorithm is designed and implemented using a 32-bit High speed processor based on FPGA. This design requires 16 clock cycle to compute QR decomposition with 15.625 M QRDs per second throughput at 250 MHz operating frequency.\",\"PeriodicalId\":144020,\"journal\":{\"name\":\"2018 International Conference on Advanced Science and Engineering (ICOASE)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Conference on Advanced Science and Engineering (ICOASE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICOASE.2018.8548895\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Advanced Science and Engineering (ICOASE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICOASE.2018.8548895","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
在无线通信系统中，多输入多输出(MIMO)等多种检测算法都需要qr分解(QRD)来实现。本文采用基于FPGA的32位高速处理器设计并实现了一种利用Gram Schmidt算法将矩阵分解为正交矩阵(Q矩阵)和上三角矩阵(R矩阵)的QRD处理器。本设计需要16个时钟周期来计算QR分解，在250 MHz工作频率下每秒吞吐量为15.625 M qrd。
The QR-decomposition (QRD) is an implementation necessary for many different detection algorithms such as MIMO (Multiple Input and Multiple Output) in wireless communication system. In this article, a QRD processor which decomposes the matrix into an orthogonal (Q matrix) and upper triangular matrix (R matrix) using Gram Schmidt algorithm is designed and implemented using a 32-bit High speed processor based on FPGA. This design requires 16 clock cycle to compute QR decomposition with 15.625 M QRDs per second throughput at 250 MHz operating frequency.
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