Songhu Ge, Hongbo Liu, Yongcai Liu, Jinling Xing, Jin Meng
{"title":"实时基带自适应数字干扰消除器的设计与实现","authors":"Songhu Ge, Hongbo Liu, Yongcai Liu, Jinling Xing, Jin Meng","doi":"10.1109/IEEE-IWS.2019.8803847","DOIUrl":null,"url":null,"abstract":"In this paper, a baseband digital canceller is designed and implemented to cancel the co-site interference. Especially, in order to achieve high-speed low-latency cancellation performance, a transposed form retimed delayed LMS (TF-RDLMS) filter structure is introduced and extended to complex signal form. In the proposed complex TF-RDLMS filter, the basic Processing Module (PM) is established with a set of real cross-coupling signal flows. Then, the canceller is implemented with Xilinx field programmable gate array (FPGA) chip by cascading several PMs. Finally, the validity and effectiveness of the implemented canceller is confirmed by experimental results. It is shown that the canceller can achieve 31 dB and 27 dB cancellation performance for 5 MHz and 10 MHz interference signal, respectively.","PeriodicalId":306297,"journal":{"name":"2019 IEEE MTT-S International Wireless Symposium (IWS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and Implementation of A Real-time Baseband Adaptive Digital Interference Canceller\",\"authors\":\"Songhu Ge, Hongbo Liu, Yongcai Liu, Jinling Xing, Jin Meng\",\"doi\":\"10.1109/IEEE-IWS.2019.8803847\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a baseband digital canceller is designed and implemented to cancel the co-site interference. Especially, in order to achieve high-speed low-latency cancellation performance, a transposed form retimed delayed LMS (TF-RDLMS) filter structure is introduced and extended to complex signal form. In the proposed complex TF-RDLMS filter, the basic Processing Module (PM) is established with a set of real cross-coupling signal flows. Then, the canceller is implemented with Xilinx field programmable gate array (FPGA) chip by cascading several PMs. Finally, the validity and effectiveness of the implemented canceller is confirmed by experimental results. It is shown that the canceller can achieve 31 dB and 27 dB cancellation performance for 5 MHz and 10 MHz interference signal, respectively.\",\"PeriodicalId\":306297,\"journal\":{\"name\":\"2019 IEEE MTT-S International Wireless Symposium (IWS)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE MTT-S International Wireless Symposium (IWS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEE-IWS.2019.8803847\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE MTT-S International Wireless Symposium (IWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEE-IWS.2019.8803847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Implementation of A Real-time Baseband Adaptive Digital Interference Canceller
In this paper, a baseband digital canceller is designed and implemented to cancel the co-site interference. Especially, in order to achieve high-speed low-latency cancellation performance, a transposed form retimed delayed LMS (TF-RDLMS) filter structure is introduced and extended to complex signal form. In the proposed complex TF-RDLMS filter, the basic Processing Module (PM) is established with a set of real cross-coupling signal flows. Then, the canceller is implemented with Xilinx field programmable gate array (FPGA) chip by cascading several PMs. Finally, the validity and effectiveness of the implemented canceller is confirmed by experimental results. It is shown that the canceller can achieve 31 dB and 27 dB cancellation performance for 5 MHz and 10 MHz interference signal, respectively.