Ken Poulton, K. Knudsen, John Kerley, James Kang, Jon Tani, Eldon Cornish, Michael VanGrouw
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We report on an analog to digital converter (ADC) system with 8 bit resolution and a sam le rate of 8 GSa/s. The system is composed of 2 thick-fh hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two differential track and hold circuits and two folding and interpolating 2 GSa/s flash digitizers. The custom memory chip accepts data at 2 GSa/s on each of two input ports, and stores the data in a 256 Kbit SUM. The ADC system uses time interleaving of 4 paths to reach 8 GSa/s and combines hardware dither with software calibration techniques to achieve 7.6 effective bits at low frequencies and 5.3 effective bits at 2 GHz input. Thick-film Hybrid
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