一个6位1GS/s低功耗闪存ADC

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI:10.1109/VDAT.2009.5158132

Yu-Chang Lien, Ying-Zu Lin, Soon-Jyh Chang

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引用次数: 14

摘要

本文提出了一种用于高速ADC的低功耗设计准则，并在0.13µm CMOS工艺中制作了一个基于该设计准则的低功耗ADC。实验结果表明，在1 GHz的采样频率下，有效比特数(ENOB)为5.16，在700MS/s的采样频率下，分辨率带宽(ERBW)高于500 MHz。由于高输入带宽和低功耗，该ADC非常适合UWB系统。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 6-bit 1GS/s low-power flash ADC

This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13µm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.

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2009 International Symposium on VLSI Design, Automation and Test

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