{"title":"高性能注入锁定分频器,采用0.18µm CMOS工艺,50 GHz LC交叉耦合振荡器","authors":"Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim","doi":"10.1109/SAPIW.2015.7237383","DOIUrl":null,"url":null,"abstract":"In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"High performance injection-locked frequency divider with 50 GHz LC cross-coupled oscillator in 0.18 µm CMOS process\",\"authors\":\"Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim\",\"doi\":\"10.1109/SAPIW.2015.7237383\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.\",\"PeriodicalId\":231437,\"journal\":{\"name\":\"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)\",\"volume\":\"141 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SAPIW.2015.7237383\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAPIW.2015.7237383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance injection-locked frequency divider with 50 GHz LC cross-coupled oscillator in 0.18 µm CMOS process
In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.