A Low-Power D-type Flip-flop with Active Inductor and Forward Body Biasing Techniques in 40-nm CMOS

A novel D-type flip-flop (DFF) with active inductive peaking powered by 0.7 V supply is proposed and implemented for low power communication. Forward bias (FB) technique is introduced for both the DFF and the active inductor in the clock buffer to effectively reduce the transistor threshold voltage, thus increasing the output swing along the data path. To mitigate the potential of junction breakdown, deep N-well NMOS is utilized for forward biasing. As the clock buffer is loaded by the active inductor, the output common-mode voltage can be increased by FB as well. The subsequent DFF can be hereby biased at class AB for fast data sampling. A pseudo random binary sequence (PRBS) generator is implemented using the proposed DFF and the active inductor to verify the low power operation. Measured results show that the PRBS-4 can generates 8 Gb/s random data stream with 1.75 pJ/bit power efficiency under a 0.7 V power supply, achieving over 2X power efficiency improvement compared to the design operating at 1.2.