{"title":"利用模糊控制系统集成代码生成","authors":"Xiaoyan Jia, Jie Guo, G. Fettweis","doi":"10.1145/1361096.1361098","DOIUrl":null,"url":null,"abstract":"High quality code generation for DSPs that consist of irregular architectures is a challenge in terms of problem complexity. Since such problems are divided into several separated subtasks in the traditional compiler backends, the code quality is decreased owing to the ignorance of the interdependencies among these subtasks. Thus, an integrated compiler backend by using fuzzy control system is developed for an irregular architecture which is called Synchronous Transfer Architecture (STA). According to the experimental results, our novel method is proved to be more efficient than the traditional method. The code size and execution time of the generated code are reduced to be about 42.7% to 62.5% of those achieved by traditional compiler backend. Moreover, the power consumption is greatly reduced concerning the efficient utilization of the STA data paths.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Integrated code generation by using fuzzy control system\",\"authors\":\"Xiaoyan Jia, Jie Guo, G. Fettweis\",\"doi\":\"10.1145/1361096.1361098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High quality code generation for DSPs that consist of irregular architectures is a challenge in terms of problem complexity. Since such problems are divided into several separated subtasks in the traditional compiler backends, the code quality is decreased owing to the ignorance of the interdependencies among these subtasks. Thus, an integrated compiler backend by using fuzzy control system is developed for an irregular architecture which is called Synchronous Transfer Architecture (STA). According to the experimental results, our novel method is proved to be more efficient than the traditional method. The code size and execution time of the generated code are reduced to be about 42.7% to 62.5% of those achieved by traditional compiler backend. Moreover, the power consumption is greatly reduced concerning the efficient utilization of the STA data paths.\",\"PeriodicalId\":375451,\"journal\":{\"name\":\"Software and Compilers for Embedded Systems\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-03-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Software and Compilers for Embedded Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1361096.1361098\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Software and Compilers for Embedded Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1361096.1361098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Integrated code generation by using fuzzy control system
High quality code generation for DSPs that consist of irregular architectures is a challenge in terms of problem complexity. Since such problems are divided into several separated subtasks in the traditional compiler backends, the code quality is decreased owing to the ignorance of the interdependencies among these subtasks. Thus, an integrated compiler backend by using fuzzy control system is developed for an irregular architecture which is called Synchronous Transfer Architecture (STA). According to the experimental results, our novel method is proved to be more efficient than the traditional method. The code size and execution time of the generated code are reduced to be about 42.7% to 62.5% of those achieved by traditional compiler backend. Moreover, the power consumption is greatly reduced concerning the efficient utilization of the STA data paths.