Regular-expression accelerators often rely on sophisticated compilers to fully exploit the available hardware capabilities for achieving wire-speed scan rates of multiple tens of gigabits per second. This paper presents a method for the efficient compilation of pattern-matching functions specified by deterministic finite automata (DFAs) into executable structures targeted at accelerators based on B-FSM programmable state machines. The compilation scheme presented is able to effectively exploit an adaptive compression mechanism to obtain one of the most compact state-transition-table structures in the industry, in combination with fast compilation times. The heuristic-based approach scales to very large DFAs having tens of millions of transitions, while achieving an approximately linear growth of the storage needs as a function of the DFA size.
{"title":"Scalable DFA Compilation for High-Performance Regular-Expression Matching","authors":"J. V. Lunteren","doi":"10.1145/2906363.2907053","DOIUrl":"https://doi.org/10.1145/2906363.2907053","url":null,"abstract":"Regular-expression accelerators often rely on sophisticated compilers to fully exploit the available hardware capabilities for achieving wire-speed scan rates of multiple tens of gigabits per second. This paper presents a method for the efficient compilation of pattern-matching functions specified by deterministic finite automata (DFAs) into executable structures targeted at accelerators based on B-FSM programmable state machines. The compilation scheme presented is able to effectively exploit an adaptive compression mechanism to obtain one of the most compact state-transition-table structures in the industry, in combination with fast compilation times. The heuristic-based approach scales to very large DFAs having tens of millions of transitions, while achieving an approximately linear growth of the storage needs as a function of the DFA size.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127337244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stefan Schürmans, Diandian Zhang, R. Leupers, G. Ascheid, Xiaotao Chen
Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.
{"title":"Improving ESL power models using switching activity information from timed functional models","authors":"Stefan Schürmans, Diandian Zhang, R. Leupers, G. Ascheid, Xiaotao Chen","doi":"10.1145/2609248.2609250","DOIUrl":"https://doi.org/10.1145/2609248.2609250","url":null,"abstract":"Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115047643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhibin Yang, J. Bodeveix, M. Filali, Kai Hu, Dian-fu Ma
SIGNAL belongs to the synchronous languages family. Such languages are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nuclear power plants. This paper reports a key step of a verified SIGNAL compiler prototype, that is the transformation from a subset of SIGNAL to S-CGA (a variant of clocked guarded actions) and the proof of semantics preservation. Compared with the existing SIGNAL compiler, we use clocked guarded actions as the intermediate representation, to integrate more synchronous programs into our verified compiler prototype in the future. However, in contrast to the SIGNAL language, clocked guarded actions can evaluate a variable even if its clock does not hold. Thus, we propose a variant of clocked guarded actions, namely S-CGA, which constrains variable accesses as done by SIGNAL. To conform with the revised semantics of clocked guarded actions, we also do some adjustments on the existing translation rules from SIGNAL to clocked guarded actions. Finally, the verified transformation is mechanized in the theorem prover Coq.
{"title":"A verified transformation: from polychronous programs to a variant of clocked guarded actions","authors":"Zhibin Yang, J. Bodeveix, M. Filali, Kai Hu, Dian-fu Ma","doi":"10.1145/2609248.2609259","DOIUrl":"https://doi.org/10.1145/2609248.2609259","url":null,"abstract":"SIGNAL belongs to the synchronous languages family. Such languages are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nuclear power plants. This paper reports a key step of a verified SIGNAL compiler prototype, that is the transformation from a subset of SIGNAL to S-CGA (a variant of clocked guarded actions) and the proof of semantics preservation. Compared with the existing SIGNAL compiler, we use clocked guarded actions as the intermediate representation, to integrate more synchronous programs into our verified compiler prototype in the future. However, in contrast to the SIGNAL language, clocked guarded actions can evaluate a variable even if its clock does not hold. Thus, we propose a variant of clocked guarded actions, namely S-CGA, which constrains variable accesses as done by SIGNAL. To conform with the revised semantics of clocked guarded actions, we also do some adjustments on the existing translation rules from SIGNAL to clocked guarded actions. Finally, the verified transformation is mechanized in the theorem prover Coq.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125584259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we address the problem of generating efficient software implementations for a large class of dataflow programs that is characterized by highly data-dependent behavior and which is therefore in general not amenable to compile-time scheduling. Previous work on implementing dataflow programs has emphasized classes of stream processing algorithms that exhibit sufficiently regular behavior to permit extensive compile-time analysis and scheduling, however many real-world stream programs, do not fall into these classes and exhibit behavior that can, for example, depend on the values and even the timing of their input data. Based on an abstract machine model, we partition the problem of implementing such programs in software into three parts, viz. reduction, composition, and code emission, and present solutions for each of them. Using the reference code of an MPEG decoder, we evaluate the resulting code quality and compare it to the state of the art compilers for the same class of stream programs, with favorable results.
{"title":"Software code generation for dynamic dataflow programs","authors":"Gustav Cedersjö, J. Janneck","doi":"10.1145/2609248.2609260","DOIUrl":"https://doi.org/10.1145/2609248.2609260","url":null,"abstract":"In this paper we address the problem of generating efficient software implementations for a large class of dataflow programs that is characterized by highly data-dependent behavior and which is therefore in general not amenable to compile-time scheduling. Previous work on implementing dataflow programs has emphasized classes of stream processing algorithms that exhibit sufficiently regular behavior to permit extensive compile-time analysis and scheduling, however many real-world stream programs, do not fall into these classes and exhibit behavior that can, for example, depend on the values and even the timing of their input data. Based on an abstract machine model, we partition the problem of implementing such programs in software into three parts, viz. reduction, composition, and code emission, and present solutions for each of them. Using the reference code of an MPEG decoder, we evaluate the resulting code quality and compare it to the state of the art compilers for the same class of stream programs, with favorable results.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130079491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bruno Bodin, Youen Lesparre, J. Delosme, Alix Munier Kordon
Dataflow modeling is a highly regarded method for the design of embedded systems. Measuring the performance of the associated analysis and compilation tools requires an efficient dataflow graph generator. This paper presents a new graph generator for Phased Computation Graphs (PCG), which augment Cyclo-Static Dataflow Graphs with both initial phases and thresholds. A sufficient condition of liveness is first extended to the PCG model. The determination of initial conditions minimizing the total amount of initial data in the channels and ensuring liveness can then be expressed using Integer Linear Programming. This contribution and other improvements of previous works are incorporated in Turbine, a new dataflow graph generator. Its effectiveness is demonstrated experimentally by comparing it to two existing generators, DFTools and SDF3.
{"title":"Fast and efficient dataflow graph generation","authors":"Bruno Bodin, Youen Lesparre, J. Delosme, Alix Munier Kordon","doi":"10.1145/2609248.2609258","DOIUrl":"https://doi.org/10.1145/2609248.2609258","url":null,"abstract":"Dataflow modeling is a highly regarded method for the design of embedded systems. Measuring the performance of the associated analysis and compilation tools requires an efficient dataflow graph generator. This paper presents a new graph generator for Phased Computation Graphs (PCG), which augment Cyclo-Static Dataflow Graphs with both initial phases and thresholds.\u0000 A sufficient condition of liveness is first extended to the PCG model. The determination of initial conditions minimizing the total amount of initial data in the channels and ensuring liveness can then be expressed using Integer Linear Programming. This contribution and other improvements of previous works are incorporated in Turbine, a new dataflow graph generator. Its effectiveness is demonstrated experimentally by comparing it to two existing generators, DFTools and SDF3.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131194115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Hausmans, Stefan J. Geuns, M. Wiggers, M. Bekooij
Real-time stream processing applications often contain multi-rate behavior. This multi-rate behavior can be accurately modeled using Synchronous Dataflow (SDF) graphs. However, no temporal analysis technique exists which is applicable for arbitrary cyclic SDF graphs and can handle cyclic resource dependencies. This paper presents a temporal analysis flow for SDF graphs which is applicable for systems with non-starvation-free schedulers such as static priority pre-emptive schedulers. The analysis flow uses an enabling rate characterization to calculate response times. This enabling rate characterization is determined using multi-dimensional periodic schedules and allows a more accurate modeling of enabling patterns than is possible with a characterization that is based on periods and enabling jitters. The presented approach is applicable for arbitrary (cyclic) graph topologies and can take buffer capacity constraints into account during analysis. Also cyclic resource dependencies can be analyzed. The presented analysis flow is the first approach that considers arbitrary SDF graph topologies in combination with cyclic resource dependencies that are caused by non-starvation-free schedulers. The proposed analysis flow is evaluated using a radio processing application. The analysis results are obtained using a tool in which the analysis flow is implemented. This case-study illustrates that the used enabling characterization achieves up to 87% better response times than with an enabling jitter based characterization.
{"title":"Temporal analysis flow based on an enabling rate characterization for multi-rate applications executed on mpsocs with non-starvation-free schedulers","authors":"J. Hausmans, Stefan J. Geuns, M. Wiggers, M. Bekooij","doi":"10.1145/2609248.2609262","DOIUrl":"https://doi.org/10.1145/2609248.2609262","url":null,"abstract":"Real-time stream processing applications often contain multi-rate behavior. This multi-rate behavior can be accurately modeled using Synchronous Dataflow (SDF) graphs. However, no temporal analysis technique exists which is applicable for arbitrary cyclic SDF graphs and can handle cyclic resource dependencies.\u0000 This paper presents a temporal analysis flow for SDF graphs which is applicable for systems with non-starvation-free schedulers such as static priority pre-emptive schedulers. The analysis flow uses an enabling rate characterization to calculate response times. This enabling rate characterization is determined using multi-dimensional periodic schedules and allows a more accurate modeling of enabling patterns than is possible with a characterization that is based on periods and enabling jitters.\u0000 The presented approach is applicable for arbitrary (cyclic) graph topologies and can take buffer capacity constraints into account during analysis. Also cyclic resource dependencies can be analyzed. The presented analysis flow is the first approach that considers arbitrary SDF graph topologies in combination with cyclic resource dependencies that are caused by non-starvation-free schedulers.\u0000 The proposed analysis flow is evaluated using a radio processing application. The analysis results are obtained using a tool in which the analysis flow is implemented. This case-study illustrates that the used enabling characterization achieves up to 87% better response times than with an enabling jitter based characterization.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128855804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This manuscript summarizes the main ideas introduced in [1]. We propose a compiler that automatically transforms a sequential application into a parallel counterpart for multicore processors. It is based on an intermediate representation, named KIR, which exposes multiple levels of parallelism and hides the complexity of the implementation details thanks to the domain-independent kernels (e.g., assignment, reduction). The effectiveness and performance of our approach, built on top of GCC, has been tested with a large variety of codes.
{"title":"A parallelizing compiler for multicore systems","authors":"","doi":"10.1145/2609248.2609254","DOIUrl":"https://doi.org/10.1145/2609248.2609254","url":null,"abstract":"This manuscript summarizes the main ideas introduced in [1]. We propose a compiler that automatically transforms a sequential application into a parallel counterpart for multicore processors. It is based on an intermediate representation, named KIR, which exposes multiple levels of parallelism and hides the complexity of the implementation details thanks to the domain-independent kernels (e.g., assignment, reduction). The effectiveness and performance of our approach, built on top of GCC, has been tested with a large variety of codes.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114592255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sara Elshobaky, A. El-Mahdy, Erven Rohou, Layla A. A. El-Sayed, Mohamed Nazih ElDerini
Embedded systems such as mobile devices are currently ubiquitous. The performance potential of these devices is rapidly improving by incorporating multi-core and GPU technologies, and is rapidly catching up with the workstation platforms. Nevertheless, the heterogeneity of the underlying hardware as well as the low-power constraints severely limit performance portability. In this paper we consider the case of leveraging JIT compilers to provide portable parallelization while hiding the corresponding expensive runtime analysis. We propose a novel lightweight JIT framework that exploits the device idle time and the large storage space generally available on these devices. The framework performs 'incremental' analysis while the processor is idle (such as during charging time), and exploits the storage space to cache intermediate analysis results. Such approach requires reengineering existing complex optimization analysis methods. For this paper, we focus on the traditional loop parallelization analysis, and implement a working prototype into the LLVM framework, integrating a lightweight dynamic profiling method to identify hotspots. Initial results demonstrate the low overhead of our method for parallelizing simple loops on an embedded GPU.
{"title":"A lightweight incremental analysis and profiling framework for embedded devices","authors":"Sara Elshobaky, A. El-Mahdy, Erven Rohou, Layla A. A. El-Sayed, Mohamed Nazih ElDerini","doi":"10.1145/2609248.2609263","DOIUrl":"https://doi.org/10.1145/2609248.2609263","url":null,"abstract":"Embedded systems such as mobile devices are currently ubiquitous. The performance potential of these devices is rapidly improving by incorporating multi-core and GPU technologies, and is rapidly catching up with the workstation platforms. Nevertheless, the heterogeneity of the underlying hardware as well as the low-power constraints severely limit performance portability. In this paper we consider the case of leveraging JIT compilers to provide portable parallelization while hiding the corresponding expensive runtime analysis. We propose a novel lightweight JIT framework that exploits the device idle time and the large storage space generally available on these devices. The framework performs 'incremental' analysis while the processor is idle (such as during charging time), and exploits the storage space to cache intermediate analysis results. Such approach requires reengineering existing complex optimization analysis methods. For this paper, we focus on the traditional loop parallelization analysis, and implement a working prototype into the LLVM framework, integrating a lightweight dynamic profiling method to identify hotspots. Initial results demonstrate the low overhead of our method for parallelizing simple loops on an embedded GPU.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123623178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Lazarescu, Albert Cohen, Adrien Guatto, Nhat Minh Lê, L. Lavagno, Antoniu Pop, M. Prieto, A. Terechko, A. Sutii
Multicore architectures are increasingly used in embedded systems to achieve higher throughput with lower energy consumption. This trend accentuates the need to convert existing sequential code to effectively exploit the resources of these architectures. We present a parallelization flow and toolset for legacy C code that includes a performance estimation tool, a parallelization tool, and a streaming-oriented parallelization framework. These are part of the work-in-progress EU FP7 PHARAON project that aims to develop a complete set of techniques and tools to guide and assist software development for heterogeneous parallel architectures. We demonstrate the effectiveness of the use of the toolset in an experiment where we measure the parallelization quality and time for inexperienced users, and the parallelization flow and performance results for the parallelization of a practical example of a stereo vision application.
{"title":"Energy-aware parallelization flow and toolset for C code","authors":"M. Lazarescu, Albert Cohen, Adrien Guatto, Nhat Minh Lê, L. Lavagno, Antoniu Pop, M. Prieto, A. Terechko, A. Sutii","doi":"10.1145/2609248.2609264","DOIUrl":"https://doi.org/10.1145/2609248.2609264","url":null,"abstract":"Multicore architectures are increasingly used in embedded systems to achieve higher throughput with lower energy consumption. This trend accentuates the need to convert existing sequential code to effectively exploit the resources of these architectures. We present a parallelization flow and toolset for legacy C code that includes a performance estimation tool, a parallelization tool, and a streaming-oriented parallelization framework. These are part of the work-in-progress EU FP7 PHARAON project that aims to develop a complete set of techniques and tools to guide and assist software development for heterogeneous parallel architectures. We demonstrate the effectiveness of the use of the toolset in an experiment where we measure the parallelization quality and time for inexperienced users, and the parallelization flow and performance results for the parallelization of a practical example of a stereo vision application.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"733 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122938667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an exact approach to the General Offset Assignment problem arising in the domain of address code generation for application specific and digital signal processors. General Offset Assignment is composed of two subproblems, namely to find a permutation of variables in memory and to select a responsible address register for each access to one of these variables. Our method is a combination of established techniques to solve both subproblems using integer linear programming. To the best of our knowledge, it is the first approach capable of solving almost all instances of the established OffsetStone benchmark set to global optimality within reasonable time. We provide a first comprehensive evaluation of the quality of several state-of-the-art heuristics relative to the optimal solutions.
{"title":"Optimal general offset assignment","authors":"Sven Mallach, Roberto Castañeda Lozano","doi":"10.1145/2609248.2609251","DOIUrl":"https://doi.org/10.1145/2609248.2609251","url":null,"abstract":"We present an exact approach to the General Offset Assignment problem arising in the domain of address code generation for application specific and digital signal processors. General Offset Assignment is composed of two subproblems, namely to find a permutation of variables in memory and to select a responsible address register for each access to one of these variables. Our method is a combination of established techniques to solve both subproblems using integer linear programming. To the best of our knowledge, it is the first approach capable of solving almost all instances of the established OffsetStone benchmark set to global optimality within reasonable time. We provide a first comprehensive evaluation of the quality of several state-of-the-art heuristics relative to the optimal solutions.","PeriodicalId":375451,"journal":{"name":"Software and Compilers for Embedded Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114703091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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