{"title":"现实故障建模的闪存测试[j]","authors":"A. Keshk","doi":"10.1109/ICEEC.2004.1374512","DOIUrl":null,"url":null,"abstract":"Bridging faults and fault disturbances models ofjlash memories are presented in this work. Simulation results show that some of bridging faults are cause disturbances to the same row or column cells. New test algorithm for testing bridging faults and disturbances are proposed. The test length of the proposed method is shorter than the previous methods, which considered only disturbance faults.","PeriodicalId":180043,"journal":{"name":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Flash memory testing for realistic fault modeling ICEEC2004\",\"authors\":\"A. Keshk\",\"doi\":\"10.1109/ICEEC.2004.1374512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Bridging faults and fault disturbances models ofjlash memories are presented in this work. Simulation results show that some of bridging faults are cause disturbances to the same row or column cells. New test algorithm for testing bridging faults and disturbances are proposed. The test length of the proposed method is shorter than the previous methods, which considered only disturbance faults.\",\"PeriodicalId\":180043,\"journal\":{\"name\":\"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEC.2004.1374512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEC.2004.1374512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Flash memory testing for realistic fault modeling ICEEC2004
Bridging faults and fault disturbances models ofjlash memories are presented in this work. Simulation results show that some of bridging faults are cause disturbances to the same row or column cells. New test algorithm for testing bridging faults and disturbances are proposed. The test length of the proposed method is shorter than the previous methods, which considered only disturbance faults.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
