1.28 μ m/sup非接触式存储单元技术，用于3v - 64mbit EEPROM

1992 International Technical Digest on Electron Devices Meeting Pub Date : 1900-01-01 DOI:10.1109/IEDM.1992.307524

H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, N. Miyamoto, S. Saeki, Y. Ohji, M. Ushiyama, J. Yugami, T. Morimoto, T. Nishida

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引用次数: 7

摘要

本文介绍了一种新颖的非接触式存储单元技术，用于3v - 64Mbit的NOR结构EEPROM。利用Fowler-Nordheim隧道机制开发了一种新的程序/擦除方案，从而实现单3V电源运行。该方案还改善了存储阵列中“低电平”阈值电压的散射问题，该问题严重影响了NOR结构中降低V/sub /c时的读操作余量。基于0.4 μ m的CMOS工艺，采用非接触式存储单元技术，成功实现了1.28 μ m/sup /的小单元面积，具有64Mbit的集成能力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM

This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in "low-level" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<>

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1992 International Technical Digest on Electron Devices Meeting

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