{"title":"四值逻辑与开关级的差异","authors":"Mou Hu","doi":"10.1109/ISMVL.1994.302177","DOIUrl":null,"url":null,"abstract":"In this paper, the application of a four-valued logic to the switch-level test generation is studied. A switch-level operator fault model is proposed. Switch-level U difference and Z difference of a function to a fault are defined. A method to derive switch-level differences is given. Finally, a new switch-level test generation algorithm for CMOS circuits is presented.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A four-valued logic and switch-level differences\",\"authors\":\"Mou Hu\",\"doi\":\"10.1109/ISMVL.1994.302177\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the application of a four-valued logic to the switch-level test generation is studied. A switch-level operator fault model is proposed. Switch-level U difference and Z difference of a function to a fault are defined. A method to derive switch-level differences is given. Finally, a new switch-level test generation algorithm for CMOS circuits is presented.<<ETX>>\",\"PeriodicalId\":137138,\"journal\":{\"name\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"volume\":\"228 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1994.302177\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1994.302177","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, the application of a four-valued logic to the switch-level test generation is studied. A switch-level operator fault model is proposed. Switch-level U difference and Z difference of a function to a fault are defined. A method to derive switch-level differences is given. Finally, a new switch-level test generation algorithm for CMOS circuits is presented.<>
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