Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302199
Y. Yuminaka, T. Aoki, T. Higuchi
Investigates new architecture LSIs based on wave-parallel computing (WPC) to address the interconnection problems in highly parallel VLSI systems. The underlying concept is frequency multiplexing of digital signals, which enables the utilization of the parallelism of electrical (or optical) waves for parallel processing. The key to success with WPC architecture lies in finding efficient implementation of multi-wave selection function. The paper proposes a multi-wave selection circuit based on coherent detection of modulated waves. The proposed method has potential advantage of high degree of multiplexing and real-time-variable selectivity. Also, its application to the densely connected WPC architecture for minimum-latency image processing is discussed with emphasis on the reduction in the number of interconnections.<>
{"title":"Design of wave-parallel computing circuits for densely connected architectures","authors":"Y. Yuminaka, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.1994.302199","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302199","url":null,"abstract":"Investigates new architecture LSIs based on wave-parallel computing (WPC) to address the interconnection problems in highly parallel VLSI systems. The underlying concept is frequency multiplexing of digital signals, which enables the utilization of the parallelism of electrical (or optical) waves for parallel processing. The key to success with WPC architecture lies in finding efficient implementation of multi-wave selection function. The paper proposes a multi-wave selection circuit based on coherent detection of modulated waves. The proposed method has potential advantage of high degree of multiplexing and real-time-variable selectivity. Also, its application to the densely connected WPC architecture for minimum-latency image processing is discussed with emphasis on the reduction in the number of interconnections.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116700767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302208
A. Kaviani, Z. Vranesic
Proposes an algorithm for processor partitioning in multiprocessor systems. The algorithm is based on fuzzy logic. It takes crisp inputs that represent the remaining amount of work and the efficiency of an application and produces the output that determines the number of processors that are to be allocated to the application during a given reallocation period. Simulation results are presented that indicate the effectiveness of the proposed scheme.<>
{"title":"On scheduling in multiprocessor systems using fuzzy logic","authors":"A. Kaviani, Z. Vranesic","doi":"10.1109/ISMVL.1994.302208","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302208","url":null,"abstract":"Proposes an algorithm for processor partitioning in multiprocessor systems. The algorithm is based on fuzzy logic. It takes crisp inputs that represent the remaining amount of work and the efficiency of an application and produces the output that determines the number of processors that are to be allocated to the application during a given reallocation period. Simulation results are presented that indicate the effectiveness of the proposed scheme.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123455749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302222
Yeong-Jar Chang, Chung-Len Lee
This paper presents a new scheme for synthesizing any multi-variable MVL (Multi-Valued Logic) function. The scheme utilizes a hybrid approach, i.e. a combination of the current mode and the voltage mode CMOS circuits, to synthesize MVL functions. Due to better utilization of circuit components, it can reduce the transistor count (cost) of the synthesized circuits about one half as compared with those using the MIN-MAX gates and literals or the T-gates. Also, an extra noise margin added in the design eliminates the need of the threshold detection circuit to recover the signal in this scheme.<>
{"title":"Synthesis of multi-variable MVL functions using hybrid mode CMOS logic","authors":"Yeong-Jar Chang, Chung-Len Lee","doi":"10.1109/ISMVL.1994.302222","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302222","url":null,"abstract":"This paper presents a new scheme for synthesizing any multi-variable MVL (Multi-Valued Logic) function. The scheme utilizes a hybrid approach, i.e. a combination of the current mode and the voltage mode CMOS circuits, to synthesize MVL functions. Due to better utilization of circuit components, it can reduce the transistor count (cost) of the synthesized circuits about one half as compared with those using the MIN-MAX gates and literals or the T-gates. Also, an extra noise margin added in the design eliminates the need of the threshold detection circuit to recover the signal in this scheme.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114309428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302183
B. Fei, Q. Hong, Gongli Zhang
A new approach to identify the linear ternary logic functions is introduced. It is easy to know if a ternary function is linear using its truth-valued vector and three-three compression algorithm presented in this paper. The algebraic expression of the linear logic function given by its truth-valued vector can be derived from the three-three compression algorithm.<>
{"title":"Identification of linear ternary logic functions and its algorithms","authors":"B. Fei, Q. Hong, Gongli Zhang","doi":"10.1109/ISMVL.1994.302183","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302183","url":null,"abstract":"A new approach to identify the linear ternary logic functions is introduced. It is easy to know if a ternary function is linear using its truth-valued vector and three-three compression algorithm presented in this paper. The algebraic expression of the linear logic function given by its truth-valued vector can be derived from the three-three compression algorithm.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302211
Hao Tang, H. Lin, Sen Jung Wei
In contrast to conventional CMOS and bipolar implementations for fuzzifier hardwares, the newly proposed fuzzifier circuits take advantage of the unique folding characteristic of one class of quantum well device, namely, the resonant tunneling diode (RTD). Three different types of RTD based fuzzifiers are proposed depending on the kinds of intrinsic I-V characteristics available. For fuzzy logic purposes, the multi-peaked RTD I-V characteristics can be generally classified as triangular, sawtooth and hysteretic types. The speed of operation, i.e. fuzzy logic inference per second (FLIPS) is expected to be high, and circuit complexity is reduced with respect to previously proposed fuzzifier circuits using conventional devices such as CMOS.<>
{"title":"Multi-peak resonant tunneling diodes based fuzzifiers","authors":"Hao Tang, H. Lin, Sen Jung Wei","doi":"10.1109/ISMVL.1994.302211","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302211","url":null,"abstract":"In contrast to conventional CMOS and bipolar implementations for fuzzifier hardwares, the newly proposed fuzzifier circuits take advantage of the unique folding characteristic of one class of quantum well device, namely, the resonant tunneling diode (RTD). Three different types of RTD based fuzzifiers are proposed depending on the kinds of intrinsic I-V characteristics available. For fuzzy logic purposes, the multi-peaked RTD I-V characteristics can be generally classified as triangular, sawtooth and hysteretic types. The speed of operation, i.e. fuzzy logic inference per second (FLIPS) is expected to be high, and circuit complexity is reduced with respect to previously proposed fuzzifier circuits using conventional devices such as CMOS.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129734549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302188
Hui Min Wang, Chung-Len Lee, Jwu-E Chen
A complete test set (CTS) is defined and derived for multiple-valued logic (MVL) Min/Max networks. The CTS can detect any single and multiple stuck-at faults of the MVL Min/Max network regardless of its implementation. Two splitting algorithms to generate the CTS or a given MVL function are proposed. One algorithm demonstrates over 2 orders speed improvement and 3 orders memory savings and the other algorithm demonstrates over 4 orders speed improvement and 2 orders memory savings with respect to the conventional truth table enumerating method.<>
{"title":"Complete test set for multiple-valued logic networks","authors":"Hui Min Wang, Chung-Len Lee, Jwu-E Chen","doi":"10.1109/ISMVL.1994.302188","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302188","url":null,"abstract":"A complete test set (CTS) is defined and derived for multiple-valued logic (MVL) Min/Max networks. The CTS can detect any single and multiple stuck-at faults of the MVL Min/Max network regardless of its implementation. Two splitting algorithms to generate the CTS or a given MVL function are proposed. One algorithm demonstrates over 2 orders speed improvement and 3 orders memory savings and the other algorithm demonstrates over 4 orders speed improvement and 2 orders memory savings with respect to the conventional truth table enumerating method.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127335449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302191
Jin-Zhao Wu, Hongyan Tan
We show that there is a polynomial over the rational number field Q corresponding to a given propositional formula in a given many-valued logic. Then, to decide whether a propositional formula can be deduced from a finite set of such formulas (deduction problem), we only need to decide whether the polynomial vanishes on an algebraic variety which is related to this formula set. By decomposing this algebraic variety, an algorithm to decide this problem is given.<>
{"title":"An algebraic method to decide the deduction problem in many-valued propositional calculus","authors":"Jin-Zhao Wu, Hongyan Tan","doi":"10.1109/ISMVL.1994.302191","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302191","url":null,"abstract":"We show that there is a polynomial over the rational number field Q corresponding to a given propositional formula in a given many-valued logic. Then, to decide whether a propositional formula can be deduced from a finite set of such formulas (deduction problem), we only need to decide whether the polynomial vanishes on an algebraic variety which is related to this formula set. By decomposing this algebraic variety, an algorithm to decide this problem is given.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115270845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302212
E. Pierzchala, M. Perkowski, S. Grygiel
We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from /spl plusmn/3.3 V or /spl plusmn/5 V power supplies and works in the range of frequencies up to several hundred MHz.<>
{"title":"A field programmable analog array for continuous, fuzzy, and multi-valued logic applications","authors":"E. Pierzchala, M. Perkowski, S. Grygiel","doi":"10.1109/ISMVL.1994.302212","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302212","url":null,"abstract":"We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from /spl plusmn/3.3 V or /spl plusmn/5 V power supplies and works in the range of frequencies up to several hundred MHz.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302194
G. Escalada-Imaz, F. Manyà
Testing the satisfiability of propositional Horn formulae is an important problem within artificial intelligence due to its repercussions in rule-based systems. This problem has been widely studied and its linearity has been proved for the classical case. However, nothing has been published to solve the satisfiability of multiple-valued Horn formulae, although it is closely related to deduction in expert systems frameworks (where a certainty degree is attached to each fact and rule). In this paper, we propose several new results. First, we present a calculus for multiple-valued Horn clauses and claim its soundness and completeness. Second, we offer a detailed description of an almost linear algorithm for testing the satisfiability of multiple-valued Horn formulae. Finally, the minimal model, the minimal inconsistent interpretation and the maximal set of consistent clauses are defined and furnished by another algorithm which is almost linear too. This information is particularly helpful when validating a rule-based system with a knowledge base formed by a set of multiple-valued clauses.<>
{"title":"The satisfiability problem in multiple-valued Horn formulae","authors":"G. Escalada-Imaz, F. Manyà","doi":"10.1109/ISMVL.1994.302194","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302194","url":null,"abstract":"Testing the satisfiability of propositional Horn formulae is an important problem within artificial intelligence due to its repercussions in rule-based systems. This problem has been widely studied and its linearity has been proved for the classical case. However, nothing has been published to solve the satisfiability of multiple-valued Horn formulae, although it is closely related to deduction in expert systems frameworks (where a certainty degree is attached to each fact and rule). In this paper, we propose several new results. First, we present a calculus for multiple-valued Horn clauses and claim its soundness and completeness. Second, we offer a detailed description of an almost linear algorithm for testing the satisfiability of multiple-valued Horn formulae. Finally, the minimal model, the minimal inconsistent interpretation and the maximal set of consistent clauses are defined and furnished by another algorithm which is almost linear too. This information is particularly helpful when validating a rule-based system with a knowledge base formed by a set of multiple-valued clauses.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121280042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-05-25DOI: 10.1109/ISMVL.1994.302186
Grant R. Pogosyan, A. Nozaki, M. Miyakawa, I. Rosenberg
We discuss relationships between properties and operations over the set /spl Omega/ of MVL functions. Closed properties are those invariant under the classical closure operation. A new type of properties, called hereditary, is defined, as well as hereditary closure. We calculate the ratio of hereditary properties, describe the families of maximal hereditary clones, and give a formula for their enumeration. We show that there are exactly eleven such clones in ternary logic. For Boolean algebra the lattice of all hereditary classes is finite, and we describe it completely. Meanwhile, starting from the three valued case there are still a continuum number of clones.<>
{"title":"Hereditary clones of multiple valued logic algebra","authors":"Grant R. Pogosyan, A. Nozaki, M. Miyakawa, I. Rosenberg","doi":"10.1109/ISMVL.1994.302186","DOIUrl":"https://doi.org/10.1109/ISMVL.1994.302186","url":null,"abstract":"We discuss relationships between properties and operations over the set /spl Omega/ of MVL functions. Closed properties are those invariant under the classical closure operation. A new type of properties, called hereditary, is defined, as well as hereditary closure. We calculate the ratio of hereditary properties, describe the families of maximal hereditary clones, and give a formula for their enumeration. We show that there are exactly eleven such clones in ternary logic. For Boolean algebra the lattice of all hereditary classes is finite, and we describe it completely. Meanwhile, starting from the three valued case there are still a continuum number of clones.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122184288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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