Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. Saraswat, M. Lin
{"title":"具有超薄氮化物/氧化氮化物堆叠栅电介质和预掺杂双多晶硅栅电极的高性能40 nm CMOS","authors":"Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. Saraswat, M. Lin","doi":"10.1109/IEDM.2000.904453","DOIUrl":null,"url":null,"abstract":"In this work, we report very high performance CMOS devices with 40 nm physical gate length, 12 A (EOT) nitride/oxynitride (N/O) stack gate dielectrics, and dual pre-doped poly-Si gate electrodes. The strong boron penetration resistance of the high quality N/O stack gate dielectric allows pre-doped poly gates not only for NMOS, but also for PMOS, to minimize poly depletion and improve performance. At room temperature and power supply Vdd of 1.5 V, drive currents of 1.12 mA/um for NMOS and 545 uA/um for PMOS are achieved at off-state leakage Idoff of both devices on the order of 20 nA/um. At low temperature of -50 C and proper forward body biases, those devices showed drive currents of 1.4 mA/m/um (@ 20 nA/um Idoff) for NMOS and 620 uA/um (@ 20 nA/um Idoff) for PMOS. These represent the highest 40 nm CMOS performance figures reported to date.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodes\",\"authors\":\"Q. Xiang, J. Jeon, P. Sachdey, B. Yu, K. Saraswat, M. Lin\",\"doi\":\"10.1109/IEDM.2000.904453\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we report very high performance CMOS devices with 40 nm physical gate length, 12 A (EOT) nitride/oxynitride (N/O) stack gate dielectrics, and dual pre-doped poly-Si gate electrodes. The strong boron penetration resistance of the high quality N/O stack gate dielectric allows pre-doped poly gates not only for NMOS, but also for PMOS, to minimize poly depletion and improve performance. At room temperature and power supply Vdd of 1.5 V, drive currents of 1.12 mA/um for NMOS and 545 uA/um for PMOS are achieved at off-state leakage Idoff of both devices on the order of 20 nA/um. At low temperature of -50 C and proper forward body biases, those devices showed drive currents of 1.4 mA/m/um (@ 20 nA/um Idoff) for NMOS and 620 uA/um (@ 20 nA/um Idoff) for PMOS. These represent the highest 40 nm CMOS performance figures reported to date.\",\"PeriodicalId\":276800,\"journal\":{\"name\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2000.904453\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904453","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Very high performance 40 nm CMOS with ultra-thin nitride/oxynitride stack gate dielectric and pre-doped dual poly-Si gate electrodes
In this work, we report very high performance CMOS devices with 40 nm physical gate length, 12 A (EOT) nitride/oxynitride (N/O) stack gate dielectrics, and dual pre-doped poly-Si gate electrodes. The strong boron penetration resistance of the high quality N/O stack gate dielectric allows pre-doped poly gates not only for NMOS, but also for PMOS, to minimize poly depletion and improve performance. At room temperature and power supply Vdd of 1.5 V, drive currents of 1.12 mA/um for NMOS and 545 uA/um for PMOS are achieved at off-state leakage Idoff of both devices on the order of 20 nA/um. At low temperature of -50 C and proper forward body biases, those devices showed drive currents of 1.4 mA/m/um (@ 20 nA/um Idoff) for NMOS and 620 uA/um (@ 20 nA/um Idoff) for PMOS. These represent the highest 40 nm CMOS performance figures reported to date.