W. Syafei, R. Yohena, H. Shimajiri, T. Yoshida, M. Kurosaki, Y. Nagao, B. Sai, H. Ochi
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引用次数: 4
摘要
本文介绍了在IEEE 802.11n系统上实施低密度奇偶校验(LDPC)码所带来的性能提升及其专用集成电路设计。仿真结果表明，在较高的编码率下，LDPC码比二进制卷积码的性能提高了6 dB。采用低功耗标准单元库，在0.13 μ m CMOS技术上成功完成了逻辑合成。
Performance Evaluation and ASIC Design of LDPC Decoder for IEEE802.11n
This paper presents our investigation on performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system and its Application Specific Integrated Circuit design. Simulation result shows that in higher coding rate, LDPC codes gives 6 dB better performance compared to binary convolutional codes. Logic synthesis is succesfully done on 0.13 µm CMOS technology with low-power standard cell library.
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