{"title":"N-MOSFET掺杂口袋基板的三维设计与实现","authors":"P. Saha","doi":"10.1109/ICSCAN.2018.8541208","DOIUrl":null,"url":null,"abstract":"A moderatley doped pocket is implemented in the substrate of an N-MOSFET. Three dimensional simulation modelling of the device has been carried out such that the W/L ratio can be varied. Input output characteristics of the device is obtianed from the simulation which follows the characteristics of the conventional MOSFET. In order to perfrom analysis and comparison the device designed with different channel length ranging from 20nm to 40nm, width of the device is varied from 22nm to 2um. Device characteristics are also obtained for the device with different dimension by keeping the W/L ratio constant and variable. It has been observed that for constant W/L ratio the drain current remains almost constant and for different W/L ratio the drain current changes with the same fraction as that of W/L ratio. On Being comparing the results with the conventional one this modified MOSFET gives better results in terms of both input and output characteristics. Leakage current analysis signifies that modified drain characteristics has a narrower slope.","PeriodicalId":378798,"journal":{"name":"2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Three Dimensional Design and Implementation of Doped-Pocket Substrate in N-MOSFET\",\"authors\":\"P. Saha\",\"doi\":\"10.1109/ICSCAN.2018.8541208\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A moderatley doped pocket is implemented in the substrate of an N-MOSFET. Three dimensional simulation modelling of the device has been carried out such that the W/L ratio can be varied. Input output characteristics of the device is obtianed from the simulation which follows the characteristics of the conventional MOSFET. In order to perfrom analysis and comparison the device designed with different channel length ranging from 20nm to 40nm, width of the device is varied from 22nm to 2um. Device characteristics are also obtained for the device with different dimension by keeping the W/L ratio constant and variable. It has been observed that for constant W/L ratio the drain current remains almost constant and for different W/L ratio the drain current changes with the same fraction as that of W/L ratio. On Being comparing the results with the conventional one this modified MOSFET gives better results in terms of both input and output characteristics. Leakage current analysis signifies that modified drain characteristics has a narrower slope.\",\"PeriodicalId\":378798,\"journal\":{\"name\":\"2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSCAN.2018.8541208\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCAN.2018.8541208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Three Dimensional Design and Implementation of Doped-Pocket Substrate in N-MOSFET
A moderatley doped pocket is implemented in the substrate of an N-MOSFET. Three dimensional simulation modelling of the device has been carried out such that the W/L ratio can be varied. Input output characteristics of the device is obtianed from the simulation which follows the characteristics of the conventional MOSFET. In order to perfrom analysis and comparison the device designed with different channel length ranging from 20nm to 40nm, width of the device is varied from 22nm to 2um. Device characteristics are also obtained for the device with different dimension by keeping the W/L ratio constant and variable. It has been observed that for constant W/L ratio the drain current remains almost constant and for different W/L ratio the drain current changes with the same fraction as that of W/L ratio. On Being comparing the results with the conventional one this modified MOSFET gives better results in terms of both input and output characteristics. Leakage current analysis signifies that modified drain characteristics has a narrower slope.
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