Design and Implementation on FPGA Board of a Chaos-based Stream Cipher

Chaos based stream cipher (CSC) has caught the attention of various security applications, especially for military needs and protection in Internet of Things (IoT). In fact, computing and memory resources have been suited by chaos based stream cipher for real-time communication. In this paper, we designed a chaos-based stream cipher using a robust pseudo chaotic number generator (RPCNG). The simulation of the proposed CSC is done in VHDL using the ISE Design Suite 14.6 tool of Xilinx with finite computing precision N = 32-bit and the hardware implementation is realized on the SAKURA-G FPGA board. The proposed system requires 6036 slices L UTs as hardware cost, and achieves throughput of 301.184 Mbps. It is robust against statistical attacks and thus can be used in all applications that require confidentiality.