S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama
{"title":"一个100mhz嵌入式Risc微控制器","authors":"S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama","doi":"10.1109/VLSIC.1994.586219","DOIUrl":null,"url":null,"abstract":"This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 100 Mhz Embedded Risc Microcontroller\",\"authors\":\"S. Ozaki, Y. Nishimichi, T. Kakiage, H. Yamamoto, M. Sumita, G. Inoue, M. Urano, H. Yamashita, T. Maeda, T. Nishiyama\",\"doi\":\"10.1109/VLSIC.1994.586219\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.\",\"PeriodicalId\":350730,\"journal\":{\"name\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1994.586219\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1994.586219","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper desci-ibes a lOOMHz embedded RISC microcontroller which adopts a zero-cycle branching scheme. By this scheme, two instructions are executed in a single cycle if one of them is a branch instruction. A self-clocking cache access scheme and a separated local clock generator are adopted to attain high operating frequency.