S. Sato, Koji Munakata, Masakazu Sato, N. Ueta, Yoshio Nakao, O. Nakao
{"title":"由聚酰亚胺层和三个嵌入式集成电路芯片堆叠构成的小型化印刷线路板","authors":"S. Sato, Koji Munakata, Masakazu Sato, N. Ueta, Yoshio Nakao, O. Nakao","doi":"10.1109/ESTC.2018.8546444","DOIUrl":null,"url":null,"abstract":"In the history of electronics packaging, continuous efforts have been made to achieve seemingly conflicting goals of reducing the size of electronic devices and increasing theirfunctionality. With more sophisticated packages, wearable and portable devices in particular are required to be more compact as well as reliable. To reduce the size of a package, embeddingIC (integrated circuit) chips inside is an effective solution instead of placing them on the surface. Based on this thought, we have developed a technology to produce WABE package}}$^{\\mathbf{TM}}$(wafer and board level device embedded package). The packages are produced by combining thin polyimide film layers and backgrinded IC chips. WABE Package technology has an unmatched feature thatit can reduce the footprint of a package drastically by stacking IC chips if multiple chips need to be embedded in the package. Even if the package has two or morechips, the increase in the thickness of the chip-stack structure is very limited because each layer is so thin. Another feature of the technology is parallel fabrication of each polyimide-based layer with vias filled with a conductive material for interconnection. The individual and simultaneous preparation of layers enables “one-step” colamination, which has an advantagethat only one-time press is needed even though the number of layers increases due to the chip-stack structure. This report describes the fabrication of aprototype circuit board that consists of 14 copper layers and 3 IC chips embedded vertically in them. The board is less than 0.9 mm in thickness even though it includes a large number of layers. We also report the results of various reliability testing conducted on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The prototype showed high reliability under moisture and heat test conditions simulating those in autoclave sterilization and heat-shock test conditions simulating those in the production process. These results show that the WABE Package technology that allows three chips to be embedded vertically in the package is the most promising packaging technology for extremely miniaturizing electronic circuits for medical and wearable electronics.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Miniaturized Printed Wiring Board Consisting of Polyimide Layers and Three Embedded Integrated Circuit Chips in Stacked Configuration\",\"authors\":\"S. Sato, Koji Munakata, Masakazu Sato, N. Ueta, Yoshio Nakao, O. Nakao\",\"doi\":\"10.1109/ESTC.2018.8546444\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the history of electronics packaging, continuous efforts have been made to achieve seemingly conflicting goals of reducing the size of electronic devices and increasing theirfunctionality. With more sophisticated packages, wearable and portable devices in particular are required to be more compact as well as reliable. To reduce the size of a package, embeddingIC (integrated circuit) chips inside is an effective solution instead of placing them on the surface. Based on this thought, we have developed a technology to produce WABE package}}$^{\\\\mathbf{TM}}$(wafer and board level device embedded package). The packages are produced by combining thin polyimide film layers and backgrinded IC chips. WABE Package technology has an unmatched feature thatit can reduce the footprint of a package drastically by stacking IC chips if multiple chips need to be embedded in the package. Even if the package has two or morechips, the increase in the thickness of the chip-stack structure is very limited because each layer is so thin. Another feature of the technology is parallel fabrication of each polyimide-based layer with vias filled with a conductive material for interconnection. The individual and simultaneous preparation of layers enables “one-step” colamination, which has an advantagethat only one-time press is needed even though the number of layers increases due to the chip-stack structure. This report describes the fabrication of aprototype circuit board that consists of 14 copper layers and 3 IC chips embedded vertically in them. The board is less than 0.9 mm in thickness even though it includes a large number of layers. We also report the results of various reliability testing conducted on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The prototype showed high reliability under moisture and heat test conditions simulating those in autoclave sterilization and heat-shock test conditions simulating those in the production process. These results show that the WABE Package technology that allows three chips to be embedded vertically in the package is the most promising packaging technology for extremely miniaturizing electronic circuits for medical and wearable electronics.\",\"PeriodicalId\":198238,\"journal\":{\"name\":\"2018 7th Electronic System-Integration Technology Conference (ESTC)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 7th Electronic System-Integration Technology Conference (ESTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESTC.2018.8546444\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 7th Electronic System-Integration Technology Conference (ESTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTC.2018.8546444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Miniaturized Printed Wiring Board Consisting of Polyimide Layers and Three Embedded Integrated Circuit Chips in Stacked Configuration
In the history of electronics packaging, continuous efforts have been made to achieve seemingly conflicting goals of reducing the size of electronic devices and increasing theirfunctionality. With more sophisticated packages, wearable and portable devices in particular are required to be more compact as well as reliable. To reduce the size of a package, embeddingIC (integrated circuit) chips inside is an effective solution instead of placing them on the surface. Based on this thought, we have developed a technology to produce WABE package}}$^{\mathbf{TM}}$(wafer and board level device embedded package). The packages are produced by combining thin polyimide film layers and backgrinded IC chips. WABE Package technology has an unmatched feature thatit can reduce the footprint of a package drastically by stacking IC chips if multiple chips need to be embedded in the package. Even if the package has two or morechips, the increase in the thickness of the chip-stack structure is very limited because each layer is so thin. Another feature of the technology is parallel fabrication of each polyimide-based layer with vias filled with a conductive material for interconnection. The individual and simultaneous preparation of layers enables “one-step” colamination, which has an advantagethat only one-time press is needed even though the number of layers increases due to the chip-stack structure. This report describes the fabrication of aprototype circuit board that consists of 14 copper layers and 3 IC chips embedded vertically in them. The board is less than 0.9 mm in thickness even though it includes a large number of layers. We also report the results of various reliability testing conducted on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The prototype showed high reliability under moisture and heat test conditions simulating those in autoclave sterilization and heat-shock test conditions simulating those in the production process. These results show that the WABE Package technology that allows three chips to be embedded vertically in the package is the most promising packaging technology for extremely miniaturizing electronic circuits for medical and wearable electronics.