由聚酰亚胺层和三个嵌入式集成电路芯片堆叠构成的小型化印刷线路板

S. Sato, Koji Munakata, Masakazu Sato, N. Ueta, Yoshio Nakao, O. Nakao
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引用次数: 0

摘要

在电子封装的历史上,不断的努力已经实现了减少电子设备的尺寸和增加其功能的看似矛盾的目标。随着封装越来越复杂,可穿戴和便携式设备尤其需要更加紧凑和可靠。为了减小封装的尺寸,在内部嵌入集成电路芯片是一种有效的解决方案,而不是将它们放在表面上。基于这一思想,我们开发了一种生产WABE封装}}$^{\mathbf{TM}}$(晶圆和板级器件嵌入式封装)的技术。这种封装是由聚酰亚胺薄膜层和背景IC芯片结合而成的。WABE封装技术具有无与伦比的特点,如果需要在封装中嵌入多个芯片,则可以通过堆叠IC芯片大幅减少封装的占地面积。即使封装有两个或更多的芯片,芯片堆栈结构厚度的增加是非常有限的,因为每一层都很薄。该技术的另一个特点是将每个聚酰亚胺基层与填充导电材料用于互连的过孔平行制造。单独和同时制备层可以实现“一步”叠层,其优点是即使由于芯片堆栈结构而增加层数,也只需要一次压印。本报告描述了一个原型电路板的制造,该电路板由14个铜层和3个垂直嵌入其中的IC芯片组成。虽然包含了大量的层数,但该板的厚度小于0.9毫米。我们还报告了对包装进行的各种可靠性测试的结果。这些结果是通过在一些层之间形成的菊花链图案的电测量得到的。该样机在模拟高压灭菌的湿热试验条件和模拟生产过程的热冲击试验条件下均表现出较高的可靠性。这些结果表明,可以在封装中垂直嵌入三个芯片的WABE封装技术是用于医疗和可穿戴电子产品的极小型化电子电路的最有前途的封装技术。
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Miniaturized Printed Wiring Board Consisting of Polyimide Layers and Three Embedded Integrated Circuit Chips in Stacked Configuration
In the history of electronics packaging, continuous efforts have been made to achieve seemingly conflicting goals of reducing the size of electronic devices and increasing theirfunctionality. With more sophisticated packages, wearable and portable devices in particular are required to be more compact as well as reliable. To reduce the size of a package, embeddingIC (integrated circuit) chips inside is an effective solution instead of placing them on the surface. Based on this thought, we have developed a technology to produce WABE package}}$^{\mathbf{TM}}$(wafer and board level device embedded package). The packages are produced by combining thin polyimide film layers and backgrinded IC chips. WABE Package technology has an unmatched feature thatit can reduce the footprint of a package drastically by stacking IC chips if multiple chips need to be embedded in the package. Even if the package has two or morechips, the increase in the thickness of the chip-stack structure is very limited because each layer is so thin. Another feature of the technology is parallel fabrication of each polyimide-based layer with vias filled with a conductive material for interconnection. The individual and simultaneous preparation of layers enables “one-step” colamination, which has an advantagethat only one-time press is needed even though the number of layers increases due to the chip-stack structure. This report describes the fabrication of aprototype circuit board that consists of 14 copper layers and 3 IC chips embedded vertically in them. The board is less than 0.9 mm in thickness even though it includes a large number of layers. We also report the results of various reliability testing conducted on the package. These results were obtained by electrical measurements of daisy chain patterns formed between some of the layers. The prototype showed high reliability under moisture and heat test conditions simulating those in autoclave sterilization and heat-shock test conditions simulating those in the production process. These results show that the WABE Package technology that allows three chips to be embedded vertically in the package is the most promising packaging technology for extremely miniaturizing electronic circuits for medical and wearable electronics.
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