Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654379
Z. Huang, R. Poelma, S. Vollebregt, M. H. Koelink, E. Boschman, R. Kropf, M. Gallouch, G.Q. Zhang
This article shows the fabrication process and packaging of through polymer optical vias (TPOV). The TPOV enables encapsulation and packaging of silicon photonic systems using film assisted molding (FAM) and the creation of micron-sized through polymer optical vias. The optical vias are lithographically defined in thick film photo-resist (∼ 300 μm) and parallel processed on substrate level. Placing and connecting optical windows on individual chips using pick & place is a difficult and time-consuming process because of the stringent requirements on alignment accuracy, cost and throughput. In this work we provide a solution to this problem by combining microfabrication technology with back-end film assisted molding technology for a new packaging approach for the integration of optical windows. As feasibility study we show through polymer optical windows on optical encoder Si photodiode arrays. The resulting microstructures are transparent in the spectrum of interest and hence serve as optical windows towards the substrate. Furthermore, our results show that the high aspect ratio (5:1) micro structure windows can be achieved and protected using FAM-technology. The optical through package windows are accurately defined (±5 μm accuracy due to mask limitations) and can significantly improve the throughput. The total process time of a single wafer with up to 1260 chips and 20160 windows, including lamination, exposure and development, would approximately take 1-1.5 hours.
{"title":"Wafer Level Through Polymer Optical Vias (TPOV) Enabling High Throughput of Optical Windows Manufacturing","authors":"Z. Huang, R. Poelma, S. Vollebregt, M. H. Koelink, E. Boschman, R. Kropf, M. Gallouch, G.Q. Zhang","doi":"10.1109/EPTC.2018.8654379","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654379","url":null,"abstract":"This article shows the fabrication process and packaging of through polymer optical vias (TPOV). The TPOV enables encapsulation and packaging of silicon photonic systems using film assisted molding (FAM) and the creation of micron-sized through polymer optical vias. The optical vias are lithographically defined in thick film photo-resist (∼ 300 μm) and parallel processed on substrate level. Placing and connecting optical windows on individual chips using pick & place is a difficult and time-consuming process because of the stringent requirements on alignment accuracy, cost and throughput. In this work we provide a solution to this problem by combining microfabrication technology with back-end film assisted molding technology for a new packaging approach for the integration of optical windows. As feasibility study we show through polymer optical windows on optical encoder Si photodiode arrays. The resulting microstructures are transparent in the spectrum of interest and hence serve as optical windows towards the substrate. Furthermore, our results show that the high aspect ratio (5:1) micro structure windows can be achieved and protected using FAM-technology. The optical through package windows are accurately defined (±5 μm accuracy due to mask limitations) and can significantly improve the throughput. The total process time of a single wafer with up to 1260 chips and 20160 windows, including lamination, exposure and development, would approximately take 1-1.5 hours.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123104633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546419
Juliane Föhlich, L. Dietrich, H. Oppermann, K. Lang
Trials were made for thermocompression bonding of gold contacts with different geometries. Prior to bonding, the surfaces were mechanically planarized and activated by means of an atmospheric plasma. These treatments enabled excellent shear strengths (about 50MPa) after bonding at a temperature of 160°C and a pressure of 100 MPa for short bond times (10s).
{"title":"surface treatment of gold bumps for thermocompression bonding with low temperature","authors":"Juliane Föhlich, L. Dietrich, H. Oppermann, K. Lang","doi":"10.1109/ESTC.2018.8546419","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546419","url":null,"abstract":"Trials were made for thermocompression bonding of gold contacts with different geometries. Prior to bonding, the surfaces were mechanically planarized and activated by means of an atmospheric plasma. These treatments enabled excellent shear strengths (about 50MPa) after bonding at a temperature of 160°C and a pressure of 100 MPa for short bond times (10s).","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116760489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546447
H. Kuisma, A. Cardoso, Nikolai Mäntyoja, Rüdiger Rosenkrantz, S. Nurmi, M. Gall
Fan-out wafer level packaging (FO-WLP) is the fastest growing packaging technology. Besides providing greater number of IOs than could be obtained by fan-in wafer level packaging (WLP) it also offers interesting opportunities for multi-die packaging with minimum package dimensions. Combined inertial sensor is an established category of automotive sensor components. with of two or more MEMS sensor dies for 36 axis motion measurement and an interface circuit die. It is used for electronic chassis stability control (ESC) and for advanced driver assistant systems (ADAS). Currently the sensor is packaged in various standard or proprietary configurations: ceramic cavity packages, pre-molded plastic cavity packages, over-molded SOIC, PBGA. The demand is towards smaller foot print and smaller height, lower cost and better robustness to vibrations. FO-WLP offers some excellent characteristics like small size, compatible cost, vibration robustness and low stress to sensitive MEMS dies. Present work shows that it will also reach automotive reliability requirements and pass high temperature, thermal cycle and temperature-humidity tests. Three fracture mechanism of the solder ball IOs were identified at 2000 thermal cycles. Solder fatigue was no issue and by design changes two other mechanisms can be corrected. Two-fold redundancy will make an IO failure rate low enough. EMI and internal cross-talk protection was found better than with existing devices. Reversible humidity dependence due to moisture absorption by polyimide film was seen and a lay-out change was implemented to overcome it.
{"title":"FO-WLP multi-DOF inertial sensor for automotive applications","authors":"H. Kuisma, A. Cardoso, Nikolai Mäntyoja, Rüdiger Rosenkrantz, S. Nurmi, M. Gall","doi":"10.1109/ESTC.2018.8546447","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546447","url":null,"abstract":"Fan-out wafer level packaging (FO-WLP) is the fastest growing packaging technology. Besides providing greater number of IOs than could be obtained by fan-in wafer level packaging (WLP) it also offers interesting opportunities for multi-die packaging with minimum package dimensions. Combined inertial sensor is an established category of automotive sensor components. with of two or more MEMS sensor dies for 36 axis motion measurement and an interface circuit die. It is used for electronic chassis stability control (ESC) and for advanced driver assistant systems (ADAS). Currently the sensor is packaged in various standard or proprietary configurations: ceramic cavity packages, pre-molded plastic cavity packages, over-molded SOIC, PBGA. The demand is towards smaller foot print and smaller height, lower cost and better robustness to vibrations. FO-WLP offers some excellent characteristics like small size, compatible cost, vibration robustness and low stress to sensitive MEMS dies. Present work shows that it will also reach automotive reliability requirements and pass high temperature, thermal cycle and temperature-humidity tests. Three fracture mechanism of the solder ball IOs were identified at 2000 thermal cycles. Solder fatigue was no issue and by design changes two other mechanisms can be corrected. Two-fold redundancy will make an IO failure rate low enough. EMI and internal cross-talk protection was found better than with existing devices. Reversible humidity dependence due to moisture absorption by polyimide film was seen and a lay-out change was implemented to overcome it.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546491
D. Ernst, E. Brachmann, S. Menzel, K. Bock
SAW sensors are very suitable for high temperature applications up to 1,000 °C or higher. In this work CTGS substrates were used as test sample material. To realize a sensor setup an interdigital transducer (IDT) is necessary and deposited onto the surface of CTGS. In the present work thin film deposited tungsten molybdenum (WMo) and ruthenium aluminum (RuAl) as functional chip metallization will be investigated. For electrical interconnecting of sensor dies wire bonding is the dominant technology in general. Therefore, wire bonding is also the first choice to interconnect SAW sensors. Typical wire bonding materials are Copper, Gold or Aluminum (respectively AlSi1). With regard to high temperature applications up to 1,000 °C these materials have an unsuitable melting point. With regard to reliability the homologous temperature T/Tm should be less than 0.5 i.e. the melting point of the bonding wire has to be at least around 2,275 °C. In [1] Wolfram (TS =3,422 °C) is described as suitable wire material, but it is not common for wire bonding at present. Platinum (TS =1,768 °C) is the best fitting material which is available as adequate bonding wires at the market and already approved by wire bonding. So it is possible to use this material at least up to 748 °C for a homologous temperature of below 0.5. Another critical point besides the wire material is the chip metallization of the IDT and the antenna of the wireless SAW sensors. To reduce the thermoelectric effects at high temperatures and to improve the wire bonding process, platinum finish metallization are being investigated for both, CTGS and antenna on ceramic. For chip metallization thin film technology is used. For antenna either the thin film technology or the thick film technology can be used, while thick film technology is standard for this application. However, a combination of both technologies is applied in this paper to reach best results. Ultrasonic and Thermosonic wire bonding is also compared as main technologies for connecting the SAW chip to the antenna. In according to the DVS guideline 2811 wire pull and ball shear tests were performed on test samples to evaluate the bond quality. In publication [2] an increasing of pull strength after storage at high temperature is described. Therefore, the manufactured test samples were also stored at 800 °C for 2h and 10 h under high vacuum. The pull and shear test results are better as the initial results as expected.
{"title":"Wire Bonding of Surface Acoustic Wave (SAW) Sensors for High Temperature Applications","authors":"D. Ernst, E. Brachmann, S. Menzel, K. Bock","doi":"10.1109/ESTC.2018.8546491","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546491","url":null,"abstract":"SAW sensors are very suitable for high temperature applications up to 1,000 °C or higher. In this work CTGS substrates were used as test sample material. To realize a sensor setup an interdigital transducer (IDT) is necessary and deposited onto the surface of CTGS. In the present work thin film deposited tungsten molybdenum (WMo) and ruthenium aluminum (RuAl) as functional chip metallization will be investigated. For electrical interconnecting of sensor dies wire bonding is the dominant technology in general. Therefore, wire bonding is also the first choice to interconnect SAW sensors. Typical wire bonding materials are Copper, Gold or Aluminum (respectively AlSi1). With regard to high temperature applications up to 1,000 °C these materials have an unsuitable melting point. With regard to reliability the homologous temperature T/Tm should be less than 0.5 i.e. the melting point of the bonding wire has to be at least around 2,275 °C. In [1] Wolfram (TS =3,422 °C) is described as suitable wire material, but it is not common for wire bonding at present. Platinum (TS =1,768 °C) is the best fitting material which is available as adequate bonding wires at the market and already approved by wire bonding. So it is possible to use this material at least up to 748 °C for a homologous temperature of below 0.5. Another critical point besides the wire material is the chip metallization of the IDT and the antenna of the wireless SAW sensors. To reduce the thermoelectric effects at high temperatures and to improve the wire bonding process, platinum finish metallization are being investigated for both, CTGS and antenna on ceramic. For chip metallization thin film technology is used. For antenna either the thin film technology or the thick film technology can be used, while thick film technology is standard for this application. However, a combination of both technologies is applied in this paper to reach best results. Ultrasonic and Thermosonic wire bonding is also compared as main technologies for connecting the SAW chip to the antenna. In according to the DVS guideline 2811 wire pull and ball shear tests were performed on test samples to evaluate the bond quality. In publication [2] an increasing of pull strength after storage at high temperature is described. Therefore, the manufactured test samples were also stored at 800 °C for 2h and 10 h under high vacuum. The pull and shear test results are better as the initial results as expected.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121081880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546421
C. Schellenberg, Jörg Strogies, K. Wilke, K. Meier
In this study it was found that the HotPowCon-soldered (HPC) interconnections show another kind of ageing effects than comparable assemblies with soldered or silver-sintered joining zones. The formation of vertical cracks can observed but could not be attributed solely to the decrease in volume due to the conversion of remaining solder within the joining zone into intermetallic phases (IMC). Rather, these result from the different coefficients of thermal expansion of the selected joining partners and the joining materials themselves. The occurrence of mechanical stress within the joining zone in combination with the stiff and brittle properties of the IMP promotes the formation of the vertical cracks. In contrast to the ageing effects of soldered or silver-sintered interconnections, the HPC-soldered structures hardly impair their electrical and thermal function.
{"title":"Investigations on the high temperature suitability of diffusion soldered interconnects","authors":"C. Schellenberg, Jörg Strogies, K. Wilke, K. Meier","doi":"10.1109/ESTC.2018.8546421","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546421","url":null,"abstract":"In this study it was found that the HotPowCon-soldered (HPC) interconnections show another kind of ageing effects than comparable assemblies with soldered or silver-sintered joining zones. The formation of vertical cracks can observed but could not be attributed solely to the decrease in volume due to the conversion of remaining solder within the joining zone into intermetallic phases (IMC). Rather, these result from the different coefficients of thermal expansion of the selected joining partners and the joining materials themselves. The occurrence of mechanical stress within the joining zone in combination with the stiff and brittle properties of the IMP promotes the formation of the vertical cracks. In contrast to the ageing effects of soldered or silver-sintered interconnections, the HPC-soldered structures hardly impair their electrical and thermal function.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127440813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546499
Sri Krishna Bhogaraju, A. Hanss, M. Schmid, G. Elger, F. Conti
Silver sintering, well known in power electronic applications, is migrating into optoelectronic assembly, to replace other interconnect materials like the eutectic Au80Sn20 or SnAgCu solder. Sintering offers an interconnect that can be formed at low temperature while at the same time can operate at high temperature. The goal of the research of this paper is to develop a sintered interconnect which can replace traditional AuSn or SnAgCu (SAC) solder, offering low thermal resistance, sufficient shear strength and thermo-mechanical fatigue resistance. Silver offers excellent thermal properties and can be an effective replacement in case of low mechanical stress applications. But copper is in case of applications with high thermo-mechanical stress the material of choice due to its higher yield strength and in general due to lower material cost.Process conditions in case of silver sintering under pressure and pressureless silver sintering have been established. A stable interconnect matching the reference SAC305 solder in terms of mechanical and thermal performance has been realized returning shear strength values averaging 59MPa for silver sintering under pressure and 42MPa for pressureless sintering as against the reference SAC305 solder averaging 56MPa. The thermal performance, measured by transient thermal analysis (TTA) reveal the lower thermal resistance of 0,8K/W and 0,5K/W for silver sintering under pressure and pressureless silver sintering respectively, as against the reference SAC305 solder as expected based on the thermal conductivity of the material. Particles size, binding material, bonding force and bonding atmosphere are shown to have a major impact on the quality of the silver sintered interconnect. Pastes consisting sub-micron and nanoscale silver particles provide less porous interconnect compared to paste containing solely micron sized particles in case of pressureless sintering.A major challenge with regards to copper nano-powder based sintering is to ensure sufficient penetration of the reducing gas during the sintering process. This is observed also in terms of the mechanical (4MPa) as well as the thermal performance. The paste used in the experiments has not sufficient reducing agents. Based on the results strategies to improve the activation need to be developed for the binder chemistry.
银烧结，众所周知的电力电子应用，正在迁移到光电组装，以取代其他互连材料，如共晶Au80Sn20或SnAgCu焊料。烧结提供了一种可以在低温下形成的互连，同时可以在高温下运行。本文的研究目标是开发一种可以取代传统的AuSn或SnAgCu (SAC)焊料的烧结互连，具有低热阻，足够的剪切强度和热机械抗疲劳性。银具有优异的热性能，在低机械应力应用的情况下可以成为有效的替代品。但由于铜具有较高的屈服强度和较低的材料成本，因此在具有高热机械应力的应用中，铜是首选材料。建立了银有压烧结和无压烧结的工艺条件。在机械和热性能方面，与参考SAC305焊料匹配的稳定互连已经实现，银在有压烧结时的平均抗剪强度为59MPa，无压烧结时的平均抗剪强度为42MPa，而参考SAC305焊料的平均抗剪强度为56MPa。通过瞬态热分析(TTA)测量的热性能显示，与参考SAC305焊料相比，银在有压烧结和无压烧结的热阻分别为0.8 k /W和0.5 k /W，这是基于材料的导热性所期望的。颗粒尺寸、结合材料、结合力和结合气氛对银烧结互连体的质量有重要影响。在无压烧结的情况下，与仅含有微米级颗粒的浆料相比，由亚微米级和纳米级银颗粒组成的浆料提供更少的多孔互连。铜纳米粉烧结的一个主要挑战是在烧结过程中确保还原性气体的充分渗透。在力学(4MPa)和热性能方面也观察到这一点。实验用浆料中还原剂不足。在此基础上，需要制定提高粘合剂化学活性的策略。
{"title":"Evaluation of silver and copper sintering of first level interconnects for high power LEDs","authors":"Sri Krishna Bhogaraju, A. Hanss, M. Schmid, G. Elger, F. Conti","doi":"10.1109/ESTC.2018.8546499","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546499","url":null,"abstract":"Silver sintering, well known in power electronic applications, is migrating into optoelectronic assembly, to replace other interconnect materials like the eutectic Au80Sn20 or SnAgCu solder. Sintering offers an interconnect that can be formed at low temperature while at the same time can operate at high temperature. The goal of the research of this paper is to develop a sintered interconnect which can replace traditional AuSn or SnAgCu (SAC) solder, offering low thermal resistance, sufficient shear strength and thermo-mechanical fatigue resistance. Silver offers excellent thermal properties and can be an effective replacement in case of low mechanical stress applications. But copper is in case of applications with high thermo-mechanical stress the material of choice due to its higher yield strength and in general due to lower material cost.Process conditions in case of silver sintering under pressure and pressureless silver sintering have been established. A stable interconnect matching the reference SAC305 solder in terms of mechanical and thermal performance has been realized returning shear strength values averaging 59MPa for silver sintering under pressure and 42MPa for pressureless sintering as against the reference SAC305 solder averaging 56MPa. The thermal performance, measured by transient thermal analysis (TTA) reveal the lower thermal resistance of 0,8K/W and 0,5K/W for silver sintering under pressure and pressureless silver sintering respectively, as against the reference SAC305 solder as expected based on the thermal conductivity of the material. Particles size, binding material, bonding force and bonding atmosphere are shown to have a major impact on the quality of the silver sintered interconnect. Pastes consisting sub-micron and nanoscale silver particles provide less porous interconnect compared to paste containing solely micron sized particles in case of pressureless sintering.A major challenge with regards to copper nano-powder based sintering is to ensure sufficient penetration of the reducing gas during the sintering process. This is observed also in terms of the mechanical (4MPa) as well as the thermal performance. The paste used in the experiments has not sufficient reducing agents. Based on the results strategies to improve the activation need to be developed for the binder chemistry.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114901284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546452
A. Yuile, S. Wiese
This paper presents the application of computational fluid dynamics (CFD) in the area of electronics manufacturing technology. It focuses on the calculation of temperatures within the solder joint during reflow soldering process. The paper shows the advantages of simulation in determining temperatures that are difficult to obtain through experimental methods. Such methods should help to optimise reflow soldering processes in the electronics manufacturing industry.
{"title":"Calculation of local solder temperature profiles in reflow ovens","authors":"A. Yuile, S. Wiese","doi":"10.1109/ESTC.2018.8546452","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546452","url":null,"abstract":"This paper presents the application of computational fluid dynamics (CFD) in the area of electronics manufacturing technology. It focuses on the calculation of temperatures within the solder joint during reflow soldering process. The paper shows the advantages of simulation in determining temperatures that are difficult to obtain through experimental methods. Such methods should help to optimise reflow soldering processes in the electronics manufacturing industry.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114166635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546505
Arne Neiser, D. Seehase, Philipp Koschorrek, A. Reinhardt
For a reflow soldering process the most energy consumption is used to heat up the machine itself. If it would be possible to heat up only the solder pins to the required temperature the energy reduction will be significant. The idea behind such a process is to use a conductive heating material layer inside the printed circuit board (PCB). To generate the joule heating, it is necessary to have an electric current flow inside the heating material. This flow must be controlled, because the heating layer is a carbon-based material and can change its resistance as a function of the temperature. In this paper an experimental setup will be described, to realize a control circuit for the heating layer. First only to compensate the resistance change based on the temperature. Second a control circuit to adjust the current flow for different structures or even variable connections for each product.
{"title":"Control a Joule-Heating Embedded Layer within a Printed Circuit Board","authors":"Arne Neiser, D. Seehase, Philipp Koschorrek, A. Reinhardt","doi":"10.1109/ESTC.2018.8546505","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546505","url":null,"abstract":"For a reflow soldering process the most energy consumption is used to heat up the machine itself. If it would be possible to heat up only the solder pins to the required temperature the energy reduction will be significant. The idea behind such a process is to use a conductive heating material layer inside the printed circuit board (PCB). To generate the joule heating, it is necessary to have an electric current flow inside the heating material. This flow must be controlled, because the heating layer is a carbon-based material and can change its resistance as a function of the temperature. In this paper an experimental setup will be described, to realize a control circuit for the heating layer. First only to compensate the resistance change based on the temperature. Second a control circuit to adjust the current flow for different structures or even variable connections for each product.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124627527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546334
A. Schiffmacher, Lorenz Litzenberger, J. Wilde, V. Polezhaev, T. Huesgen
The increasing demands on power electronics with high currents and high operating temperatures has led to the establishment of ceramic substrates. More efficient heat distribution, as well as increased thermal durability, are two aspects of the superior properties of ceramic substrates compared to conventional Printed Wiring Boards (PWB). Nevertheless, there is an demand to develop new solutions based on PWBs to provide affordable and highly integrated power electronic devices for electromobility. For cost optimization, it would be advantageous to replace the hybrid technology with a single board in order to reduce materials, parts and interconnections. Unfortunately, mounting techniques like pressure-assisted silver sintering lead to damages of epoxy-glass-substrates due to high bonding pressures and high temperatures during bonding. Recent projects led to the development of high-temperature stable benzoxazin-based wiring boards. Investigations on the quality and reliability of sintered assemblies on these PWB-substrates are still pending and were systematically carried out in this work.
{"title":"Power Electronic Assemblies on Printed Wiring Boards Mounted by Silver Sintering","authors":"A. Schiffmacher, Lorenz Litzenberger, J. Wilde, V. Polezhaev, T. Huesgen","doi":"10.1109/ESTC.2018.8546334","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546334","url":null,"abstract":"The increasing demands on power electronics with high currents and high operating temperatures has led to the establishment of ceramic substrates. More efficient heat distribution, as well as increased thermal durability, are two aspects of the superior properties of ceramic substrates compared to conventional Printed Wiring Boards (PWB). Nevertheless, there is an demand to develop new solutions based on PWBs to provide affordable and highly integrated power electronic devices for electromobility. For cost optimization, it would be advantageous to replace the hybrid technology with a single board in order to reduce materials, parts and interconnections. Unfortunately, mounting techniques like pressure-assisted silver sintering lead to damages of epoxy-glass-substrates due to high bonding pressures and high temperatures during bonding. Recent projects led to the development of high-temperature stable benzoxazin-based wiring boards. Investigations on the quality and reliability of sintered assemblies on these PWB-substrates are still pending and were systematically carried out in this work.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130595575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/ESTC.2018.8546478
J. Řeboun, J. Hlina, R. Soukup, J. Johan
This paper presents a research focused on development of a new technology for the realization of substrates for power applications such as LED and power modules or CPV receivers. Power electronics puts high demands on substrates and electrical interconnections in terms of high current density in conductors and high dielectric strength and thermal conductivity of insulators. New thick printed copper technology is a selective additive manufacturing process that brings the benefits of material savings and production no chemical waste. It also brings significantly higher pattern resolution (down to 100 $mu$ m line/gap) than conventional DBC technology, possibility to realize step & relief thickness profile, Cu plated vias and multilayer circuits capability. Thick printed copper films show sufficient adhesion to alumina and aluminium nitride substrates and have an excellent resistance to thermal shock cycling.
{"title":"Printed thick copper films for power applications","authors":"J. Řeboun, J. Hlina, R. Soukup, J. Johan","doi":"10.1109/ESTC.2018.8546478","DOIUrl":"https://doi.org/10.1109/ESTC.2018.8546478","url":null,"abstract":"This paper presents a research focused on development of a new technology for the realization of substrates for power applications such as LED and power modules or CPV receivers. Power electronics puts high demands on substrates and electrical interconnections in terms of high current density in conductors and high dielectric strength and thermal conductivity of insulators. New thick printed copper technology is a selective additive manufacturing process that brings the benefits of material savings and production no chemical waste. It also brings significantly higher pattern resolution (down to 100 $mu$ m line/gap) than conventional DBC technology, possibility to realize step & relief thickness profile, Cu plated vias and multilayer circuits capability. Thick printed copper films show sufficient adhesion to alumina and aluminium nitride substrates and have an excellent resistance to thermal shock cycling.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123979502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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