Charge trapping effects on Metal-Gate/High-k/III-V MOS devices assessed through C-V hysteresis

In this work, the differences in the trap-ping/detrapping characteristics of Metal-Gate/High-k/III-V MOS stacks is experimentally studied by means of the C-V Hysteresis and dynamic stress. Samples under study include the combination of n-InP and n-InGaAs substrates with HfO2 or Al2O3 dielectrics as gate oxides. This allows to assess the impact of both the substrate and the dielectric on the quality of the complete structure. Results show that Al2O3-based stacks exhibit lower overall trapped charge during hysteresis cycles than their HfO2 counterparts. Additionally, InP-based samples introduce a larger amount of defects above the fermi-level when compared to InGaAs samples for positive stress, but with negligible trapping effects when stressing towards inversion, which is a positive indicator in terms of reliability.