Pub Date : 2017-07-01DOI: 10.1109/CAMTA.2017.8058132
Elodie Tiouchichine, M. S. Haro, X. Bertou, Horacio Amaldi, M. G. Berisso, J. Blostein, J. Tiffenberg, M. Pérez, Sergio Suárez, G. F. Moroni
Thick Charge Couple Devices have proven to be interesting particle detectors. The DAMIC and CONNIE collaborations are using this technology to search for the elastic scattering of a dark matter particle or a neutrino with a silicon nucleus, producing a nuclear recoil. The experiments reach unprecedented sensitivity at low energies (below 100 eV) by taking advantage of the low readout noise achieved by these devices. The present document describes an experimental setup at the Centra Atomico Bariloche, its noise treatment and its calibration.
{"title":"Setup and calibration of a particle detector based on charge coupled devices","authors":"Elodie Tiouchichine, M. S. Haro, X. Bertou, Horacio Amaldi, M. G. Berisso, J. Blostein, J. Tiffenberg, M. Pérez, Sergio Suárez, G. F. Moroni","doi":"10.1109/CAMTA.2017.8058132","DOIUrl":"https://doi.org/10.1109/CAMTA.2017.8058132","url":null,"abstract":"Thick Charge Couple Devices have proven to be interesting particle detectors. The DAMIC and CONNIE collaborations are using this technology to search for the elastic scattering of a dark matter particle or a neutrino with a silicon nucleus, producing a nuclear recoil. The experiments reach unprecedented sensitivity at low energies (below 100 eV) by taking advantage of the low readout noise achieved by these devices. The present document describes an experimental setup at the Centra Atomico Bariloche, its noise treatment and its calibration.","PeriodicalId":383970,"journal":{"name":"2017 Argentine Conference of Micro-Nanoelectronics, Technology and Applications (CAMTA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/CAMTA.2017.8058135
S. Pazos, F. Aguirre, F. Palumbo
In this work, the differences in the trap-ping/detrapping characteristics of Metal-Gate/High-k/III-V MOS stacks is experimentally studied by means of the C-V Hysteresis and dynamic stress. Samples under study include the combination of n-InP and n-InGaAs substrates with HfO2 or Al2O3 dielectrics as gate oxides. This allows to assess the impact of both the substrate and the dielectric on the quality of the complete structure. Results show that Al2O3-based stacks exhibit lower overall trapped charge during hysteresis cycles than their HfO2 counterparts. Additionally, InP-based samples introduce a larger amount of defects above the fermi-level when compared to InGaAs samples for positive stress, but with negligible trapping effects when stressing towards inversion, which is a positive indicator in terms of reliability.
{"title":"Charge trapping effects on Metal-Gate/High-k/III-V MOS devices assessed through C-V hysteresis","authors":"S. Pazos, F. Aguirre, F. Palumbo","doi":"10.1109/CAMTA.2017.8058135","DOIUrl":"https://doi.org/10.1109/CAMTA.2017.8058135","url":null,"abstract":"In this work, the differences in the trap-ping/detrapping characteristics of Metal-Gate/High-k/III-V MOS stacks is experimentally studied by means of the C-V Hysteresis and dynamic stress. Samples under study include the combination of n-InP and n-InGaAs substrates with HfO2 or Al2O3 dielectrics as gate oxides. This allows to assess the impact of both the substrate and the dielectric on the quality of the complete structure. Results show that Al2O3-based stacks exhibit lower overall trapped charge during hysteresis cycles than their HfO2 counterparts. Additionally, InP-based samples introduce a larger amount of defects above the fermi-level when compared to InGaAs samples for positive stress, but with negligible trapping effects when stressing towards inversion, which is a positive indicator in terms of reliability.","PeriodicalId":383970,"journal":{"name":"2017 Argentine Conference of Micro-Nanoelectronics, Technology and Applications (CAMTA)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123333900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/CAMTA.2017.8058133
R. S. Raphael, M. P. Agord, Leandro Tiago Manera, C. M. Chagas, S. Finco
This work summarizes the set of building and operating features for a third-order Charge Pump Phase-Locked Loop CP-PLL-based Frequency Synthesizer for clock generation. For implementation purpose, a derived architectural solution for N integer frequency division is proposed considering the particular design requirements in the PLL programmability. Additionally, from the set of reference design equations, a derived set of models are proposed for Low Pass Filter LPF design, considering the voltage controlled oscillator VCO input capacitance effects. From the PLL settings at simulation environment, circuit level results indicate a settling time TS < 2 μs, considering the divide ratio N variation (8–16).
{"title":"Programmable PLL-based frequency synthesizer: Modeling and design considerations","authors":"R. S. Raphael, M. P. Agord, Leandro Tiago Manera, C. M. Chagas, S. Finco","doi":"10.1109/CAMTA.2017.8058133","DOIUrl":"https://doi.org/10.1109/CAMTA.2017.8058133","url":null,"abstract":"This work summarizes the set of building and operating features for a third-order Charge Pump Phase-Locked Loop CP-PLL-based Frequency Synthesizer for clock generation. For implementation purpose, a derived architectural solution for N integer frequency division is proposed considering the particular design requirements in the PLL programmability. Additionally, from the set of reference design equations, a derived set of models are proposed for Low Pass Filter LPF design, considering the voltage controlled oscillator VCO input capacitance effects. From the PLL settings at simulation environment, circuit level results indicate a settling time TS < 2 μs, considering the divide ratio N variation (8–16).","PeriodicalId":383970,"journal":{"name":"2017 Argentine Conference of Micro-Nanoelectronics, Technology and Applications (CAMTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126312698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/CAMTA.2017.8058137
G. Salaya, M. Garcia-Inza, S. Carbonetto, A. Faigón
The offset of a Miller amplifier is mainly due to an imperfect matching between its inputs. When the input transistors are MOSFETs, the exposure to ionizing radiation affect the threshold voltage of both transistors. With proper polarization, the shift in the threshold voltage impoverishes the matching in the input, increasing the offset. Hence, measuring the change in the offset during irradiation, one can estimate the absorbed radiation dose. In this work, a theoretical analysis is presented in order to establish the effect of ionizing radiation on the different blocks of the Miller amplifier. The design of a Miller amplifier and its fabrication on an integrated circuit for testing is described. The design and assembly of a dedicated hardware and software for data acquisition is also described. First results on the fabricated dosimeter in a 0.6μm commercial CMOS technology show a sensitivity of 60 mV/Gy and a resolution of 4 cGy.
{"title":"Design and characterization of a CMOS two-stage miller amplifier for ionizing radiation dosimetry","authors":"G. Salaya, M. Garcia-Inza, S. Carbonetto, A. Faigón","doi":"10.1109/CAMTA.2017.8058137","DOIUrl":"https://doi.org/10.1109/CAMTA.2017.8058137","url":null,"abstract":"The offset of a Miller amplifier is mainly due to an imperfect matching between its inputs. When the input transistors are MOSFETs, the exposure to ionizing radiation affect the threshold voltage of both transistors. With proper polarization, the shift in the threshold voltage impoverishes the matching in the input, increasing the offset. Hence, measuring the change in the offset during irradiation, one can estimate the absorbed radiation dose. In this work, a theoretical analysis is presented in order to establish the effect of ionizing radiation on the different blocks of the Miller amplifier. The design of a Miller amplifier and its fabrication on an integrated circuit for testing is described. The design and assembly of a dedicated hardware and software for data acquisition is also described. First results on the fabricated dosimeter in a 0.6μm commercial CMOS technology show a sensitivity of 60 mV/Gy and a resolution of 4 cGy.","PeriodicalId":383970,"journal":{"name":"2017 Argentine Conference of Micro-Nanoelectronics, Technology and Applications (CAMTA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134228027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/CAMTA.2017.8058136
A. Fontana, S. Pazos, F. Aguirre, F. Palumbo
This work presents a SPICE-based automatic SET sensitivity evaluation of a 180nm CMOS full-custom Operational Amplifier. The set-up uses the well known double exponential current law to inject SET into every sensitive node in the circuit hierarchy. The pulse parameters are obtained according to a previously generated population of particles with randomly assigned energies and species, the node bias condition at the instant of the strike and an empirical model obtained through TCAD simulations. The circuit is evaluated transistor-wise for each ion of the generated database and the output waveforms are processed in time and frequency domain to obtain figures of merit of the hardness of the proposed design on a given radioactive environment. Results allow to identify the most sensitive devices and the expected error rate for the projected application, allowing to conduct hardening techniques during early design stages.
{"title":"Automatic ASET sensitivity evaluation of a custom-designed 180nm CMOS technology operational amplifier","authors":"A. Fontana, S. Pazos, F. Aguirre, F. Palumbo","doi":"10.1109/CAMTA.2017.8058136","DOIUrl":"https://doi.org/10.1109/CAMTA.2017.8058136","url":null,"abstract":"This work presents a SPICE-based automatic SET sensitivity evaluation of a 180nm CMOS full-custom Operational Amplifier. The set-up uses the well known double exponential current law to inject SET into every sensitive node in the circuit hierarchy. The pulse parameters are obtained according to a previously generated population of particles with randomly assigned energies and species, the node bias condition at the instant of the strike and an empirical model obtained through TCAD simulations. The circuit is evaluated transistor-wise for each ion of the generated database and the output waveforms are processed in time and frequency domain to obtain figures of merit of the hardness of the proposed design on a given radioactive environment. Results allow to identify the most sensitive devices and the expected error rate for the projected application, allowing to conduct hardening techniques during early design stages.","PeriodicalId":383970,"journal":{"name":"2017 Argentine Conference of Micro-Nanoelectronics, Technology and Applications (CAMTA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125498181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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