Design and Investigation of Configurable Source Coupled Logic

This paper introduces and investigates a configurable source coupled logic (cSCL) by configuring the bulk connection of the PMOS load transistor. In the low-power mode configuration, the circuit operates in weak inversion (i.e. subthreshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its drain. However, in the highspeed mode configuration, the circuit operates in strong inversion (i.e. above threshold) regime, hence, its bulk connection of the PMOS load transistor is connected to its source. We have designed a 3-input XOR gate using the standard CMOS, STSCL, SCL, and cSCl using a 65 nm CMOS technology. Simulations demonstrated that, by configuring the cSCL in the low-power mode, it can operate up to 4X faster than standard CMOS and by configuring the cSCL in the high-speed, it can provide a power reduction of 62.46% compared to the standard CMOS.