CMOS三元电路的可测试性分析

[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic Pub Date : 1991-05-26 DOI:10.1109/ISMVL.1991.130722

C. Rozon, H. Mouftah

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引用次数: 1

摘要

为了找到合适的测试向量来检测卡通、卡开和卡短故障，研究了三元CMOS门的可测试性。采用两级故障模型方法:低元件数算符采用晶体管级故障模型，大元件数算符采用门级故障模型。每个门的结果以表格形式给出。因为与类似的CMOS二进制电路相比，这些三元CMOS电路在集合(0,1,2)上操作

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Testability analysis of CMOS ternary circuits

The testability of ternary CMOS gates was examined in order to find suitable test vectors to detect stuck-at, stuck-open, and stuck-short faults. A two-level fault model approach was used: a transistor-by-transistor model for low component count operators and a gate-level model for large component count operators. Results are given in a tabular format for each gate. Since these ternary CMOS circuits operate on the set (0,1,2) compared to similar CMOS binary circuits which operate on the set

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[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic

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