Low-power methodology issues in digital circuit design

Two circuit implementations were considered. First, the VHDL description of a matched filter was synthesized, and the design was completed with a place&route tool. Second, a full-custom circuit was designed with the same structure to compare the power dissipation of the circuits. A low-power flip-flop is introduced. Both circuits were extensively simulated with several 0.35 /spl mu/m transistor models, different supply voltages, netlists including parasitic data, and temperature range of -55 to +125 degrees. The full-custom circuit consumed 25% of the power of the standard-cell circuit.