Timing analysis for wide IO memory interface applications with silicon interposer

Memory bandwidth requirements for future high-end applications such as graphics, 200G/400G networking and high performance computing is driving the need for more “on-chip memory”. Silicon Interposer based 2.5D integration provides an intermediate path to achieving high memory bandwidth by integrating memory in package. This paper discusses timing budget analysis for realizing wide IO memory interfaces in silicon interposer technology. Traditional signal and power integrity (SI/PI) analysis for closing system timing in DDR interfaces cannot be applied directly to “chip-to-chip scenarios” as it tends to be time consuming because of need for extensive electromagnetic (EM) simulations. In addition, the assumptions on bus activity and IO bandwidth/density/speed are unique to 2.5D memory customer applications. Applying traditional assumptions from off-chip double data rate (DDR) memory interfaces to “in-package” memory interfaces can lead to additional cost overhead at chip/package and board level. The key contributions of this paper are in providing an accurate time efficient SPICE based modeling methodology to design and optimize 2.5D memory applications cost effectively to meet desired timing specifications. This paper notes simultaneous switching noise (SSN) to be a major impairment leading to eye closure in wide memory interfaces with worst case timing jitter numbers of the order of 130ps in FPGA applications. Achieving 500MHz to 1GHz DDR operating speeds primarily require a more rigorous application - based tuning of on-die decoupling capacitance, PDN inductive parasitics, interconnect length and IO drive strength. But the power, bandwidth and latency benefits of wide IO system-in-package (SIP) memory make the additional development effort worthwhile.